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features ? high-performance, low-power atmel ? avr ? xmega ? 8/16-bit microcontroller ? non-volatile program and data memories ? 64k - 256kbytes of in-system self-programmable flash ? 4k - 8kbytes boot section ? 2k - 4kbytes eeprom ? 4k - 16kbytes internal sram ? peripheral features ? four-channel dma controller ? eight-channel event system ? seven 16-bit timer/counters four timer/counters with 4 output compare or input capture channels three timer/counters with 2 output compare or input capture channels high resolution extensions on all timer/counters advanced waveform extension on one timer/counter ? one usb device interface usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compliant 32 endpoints with full configuration flexibility ? seven usarts with irda support for one usart ? aes and des crypto engine ? crc-16 (crc-ccitt) and crc-32 (ieee 802.3) generator ? two two-wire interfaces with dual address match (i 2 c and smbus compatible) ? three serial peripheral interfaces (spis) ? 16-bit real time counter with separate oscillator ? two eight-channel, 12-bit, 2ms ps analog to digital converters ? one two-channel, 12-bit, 1msps digital to analog converter ? four analog comparators with window compare function, and current source feature ? external interrupts on all general purpose i/o pins ? programmable watchdog timer with separate on-chip ultra low power oscillator ? qtouch ? library support capacitive touch buttons, sliders and wheels up to 64 sense channels ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll ? programmable multi-level interrupt controller ? five sleep modes ? programming and debug interfaces jtag (ieee 1149.1 compliant) interface, including boundary scan pdi (program and debug interface) ? i/o and packages ? 50 programmable i/o pins ? 64-lead tqfp ? 64-pad qfn ? operating voltage ? 1.6 ? 3.6v ? operating frequency ? 0 ? 12mhz from 1.6v ? 0 ? 32mhz from 2.7v typical applications ? industrial control ? climate control ? low power battery applications ? factory automation ? rf and zigbee ? power tools ? building control ? usb connectivity ? hvac ? board control ? sensor control ? utility metering ? white goods ? optical ? medical applications 8/16-bit atmel xmega a3u microcontroller ATXMEGA256A3U atxmega192a3u atxmega128a3u atxmega64a3u preliminary 8386a?avr?07/11
2 8386a?avr?07/11 xmega a3u 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restriction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?errata? on page 109 ordering code flash (bytes) eeprom (bytes) sram (bytes) speed (mhz) power supply package (1)(2)(3) temp ATXMEGA256A3U-au 256k + 8k 4k 16k 32 1.6 - 3.6v 64a -40 c - 85 c atxmega192a3u-au 192k + 8k 2k 16k atxmega128a3u-au 128k + 8k 2k 8k atxmega64a3u-au 64k + 4k 2k 4k ATXMEGA256A3U-mh 256k + 8k 4k 16k 64m2 atxmega192a3u-mh 192k + 8k 2k 16k atxmega128a3u-mh 128k + 8k 2k 8k atxmega64a3u-mh 64k + 4k 2k 4k package type 64a 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7. 65mm exposed pad, quad flat no-lead package (qfn)
3 8386a?avr?07/11 xmega a3u 2. pinout/block diagram figure 2-1. block diagram and pinout note: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 51 . power/ground digital function analog function programming, debug, test oscillator/crystal/clock general purpose i/o 1 2 3 4 64 63 62 61 60 59 58 vcc 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gnd gnd vcc avcc gnd pb0 pb1 pb3 pb2 pb7 pb5 pb4 pb6 pa7 pa6 pa0 pa1 pa2 pa3 pa4 pa5 reset/pdi pdi pr0 pr1 vdd gnd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 vcc gnd pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 vdd gnd port r event routing network data bus data bus port a adc ac0:1 port b adc dac ac0:1 aref jtag aref dma controller bus matrix sram flash ocd prog/debug interface eeprom event system controller watchdog timer watchdog osc/clk control real time counter interrupt controller sleep controller reset controller tempref vref crypto / crc cpu port e port d port c tc0:1 usart0:1 twi spi tc0:1 usart0:1 spi tc0:1 usart0:1 twi ircom usb port f tc0 usart0 spi power supervision
4 8386a?avr?07/11 xmega a3u 3. overview the atmel ? avr ? xmega ? is a family of low power, high performance and peripheral rich 8/16- bit microcontrollers based on the avr ? enhanced risc architecture. by executing instructions in a single clock cycle, the avr achieves th roughputs cpu approaching 1 million instructions per second (mips) per mhz allowing the system designer to optimize power consumption ver- sus processing speed. atmel avr cpu combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two indepen- dent registers to be accessed in one single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or cisc based microcontrollers. the xmega a3u devices provide the following features: in-system programmable flash with read-while-write capabilities, internal eep rom and sram, four-channel dma controller, eight-channel event system, programmable multi-level interrupt controller, 50 general purpose i/o pins, 16-bit real time counter, seven flexible 16-bit timer/counters with compare and pwm channels, one usb 2.0 full speed (12mbps) device interface, seven usarts, two two wire serial interfaces (twis), three serial peripheral interfaces (spis), aes and des crypto engine, two 8-channel 12-bit adcs with optional differential input with programmable gain, one 2-channel 12-bit dacs, four analog comparators with window mode, programmable watchdog timer with separate internal os cillator, accurate internal os cillators with pll and prescaler and programmable brown-out detection. the program and debug interface (pdi), a fast 2-pin interface for programming and debugging, is available. the devices also have an ieee std. 1149.1 compliant jtag test interface, and this can also be used for on-chip debug and programming. all xmega devices have five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, dma controller, event system, interrupt controller and all peripherals to continue functioning. the power-down mode saves the sram and register con- tents but stops the oscillators, disabling all other functions until the next twi or pin-change interrupt, or reset. in power-save mode, the asynchronous real time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the crystal/resonator oscillator is kept running while the rest of the device is sleeping. this allows very fast start-up from external crystal combined with low power consump- tion. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. atmel offers a free qtouch ? library for embedding capacitive touch buttons, sliders and wheels functionality into avr microcontrollers. the device is manufactured using atmel's high-density nonvolatile memory technology. the pro- gram flash memory can be reprogrammed in-system through the pdi or jtag. a bootloader running in the device can use any interface to download the application program to the flash memory. the bootloader software in the boot flash section will continue to run while the appli- cation flash section is updated, providing true read-while-write operation. by combining an 8/16-bit risc cpu with in-system self-programmable flash, the atmel xmega a3u is a pow- erful microcontroller family that provides a highly flexible and cost effective solution for embedded applications.
5 8386a?avr?07/11 xmega a3u the xmega devices are supporte d with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 block diagram figure 3-1. xmega a3u block diagram power supervision por/bod & reset port a (8) port b (8) dma controller sram adca aca dacb adcb acb ocd pdi pa[0..7] pb[0..7]/ jtag watchdog timer watchdog oscillator interrupt controller data bus prog/debug controller vcc gnd oscillator circuits/ clock generation oscillator control real time counter event system controller jtag arefa arefb pdi_data reset/ pdi_clk port b sleep controller des crc port c (8) pc[0..7] tcc0:1 usartc0:1 twic spic pd[0..7] pe[0..7] port d (8) tcd0:1 usartd0:1 spid tce0:1 usarte0:1 twie spie port e (8) aes usb port r (2) xtal1 xtal2 pr[0..1] data bus nvm controller m o r p e e h s a l f ircom bus matrix cpu tosc1 tosc2 tcf0 usartf0 pf[0..7] port f (8) event routing network to clock generator int. refs. tempref digital function analog function programming, debug, test oscillator/crystal/clock general purpose i/o
6 8386a?avr?07/11 xmega a3u 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4.1 recommended reading ?xmega ? au manual ? xmega application notes this device data sheet only contains part specific information with a short description of each peripheral and module. the xmega au manual describes the modules and peripherals in depth. the xmega application notes contain ex ample code and show applied use of the mod- ules and peripherals. all documentations are available from www.atmel.com/avr . 5. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use solution to realize touch sensitive inter- faces on most atmel avr ? microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and incl udes fully debounced reporting of touch keys and includes adja- cent key suppression ? (aks?) technology for unambiguous detection of key events. the qtouch library includes support for the qtouch and qmatrix ? acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
7 8386a?avr?07/11 xmega a3u 6. avr cpu 6.1 features ? 8/16-bit high performan ce avr risc architecture ? 142 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in sram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16mbytes of program and 16mbytes of data memory ? true 16/24-bit access to 16/24-bit i/o registers ? support for 8-, 16- and 32-bit arithmetic ? configuration change protection of system critical features 6.2 overview the atmel ? avr ? xmega ? devices use the 8/16-bit avr cpu. the main function of the cpu is to execute the code and perform all calculations. the cpu is able to access memories, perform calculations, control peripherals, and execute the program from the flash memory. interrupt handling is described in a separate section, refer to ?interrupts and programmable multi-level interrupt controller? on page 26 . figure 6-1 on page 7 shows the block diagram of the avr cpu architecture. figure 6-1. block diagram of the avr cpu architecture in order to maximize performance and parallelism, the avr uses a harvard architecture with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc-
8 8386a?avr?07/11 xmega a3u tion is pre-fetched from the program memory. this enables instructions to be executed in every clock cycle. the program memory is in-system self-programmable flash memory. 6.3 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arit hmetic and logic operations between registers or between a constant and a register. single regist er operations can also be executed. the alu operates in direct connection with all the 32 general purpose registers. in a single clock cycle, arithmetic operations between general purpose registers or between a register and an immedi- ate are executed and the result is stored back in the register file. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. the alu operations are divided into three main categories ? arithmetic, logical, and bit-func- tions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. the hardware multiplier supports signed and unsigned mul- tiplication and fractional format. 6.4 program flow after reset, the cpu starts to execute instructions from the lowest address in the flash program memory ?0?. the program counter (pc) addresses the next instruction to be fetched. after a reset, the pc is set to location ?0?. program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number uses a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. after reset the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu. 6.5 register file the register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. the register file supports the following input/output schemes: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input six of the 32 registers can be used as three 16 -bit address register pointers for data space addressing - enabling efficient address calculatio ns. one of these address pointers can also be used as an address pointer for look up tables in flash program memory.
9 8386a?avr?07/11 xmega a3u 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and bootloader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or bootloader code ? separate read/write protectio n lock bits for all sections ? crc generator support for crc check of a selectable flash program memory section ? data memory ? one linear address space ? single cycle access from cpu ? sram ? eeprom byte and page accessible optional memory mapping for direct load and store ? i/o memory configuration and status register s for all peripherals and modules 16bit-accessible general purpose regist er for global variables or flags ? bus arbitration safe and deterministic handlin g of priority between cpu, dma controller, and other bus masters ? separate buses for sram, eeprom, and i/o memory simultaneous bus access for cpu and dma controller ? production signature row memory for factory programmed data ? id for each microcontroller device type ? serial number for each device ? calibration bytes for factory calibrated peripherals ? user signature row ? one flash page in size ? can be read and written from software ? content is kept after chip erase 7.2 overview the atmel ? avr ? architecture has two main memory spaces, the program memory and the data memory. executable code can only reside in the program memory, while data can be stored both in the program memory and the data memory. the data memory includes both sram, and eeprom memory for nonvolatile data storage. all memory spaces are linear and require no memory bank switching. the available memory size configurations are shown in ?ordering information? on page 2 . in addition each device has a flash memory signature rows for calibration data, device identifica- tion, serial number etc. non volatile memory (nvm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software.
10 8386a?avr?07/11 xmega a3u 7.3 flash program memory the atmel ? avr ? xmega ? devices contain on-chip in-system reprogrammable flash mem- ory for program storage. the flash memory can be accessed for read and write both from an external programmer through the pdi, or from application software running in the device. all avr instructions are 16- or 32-bit wide, each flash address location is 16-bit. the flash memory is organized in two main sections, the application section and the boot loader section. the size of the different sections are fixed, but device dependent. these two sections have separate lock bits and can have different levels of protection. the store program memory (spm) instruction, used to write to the flash from the appl ication software, will only operate when executed from the boot loader section. the application section contains an application table section with separate lock settings. this enables safe storage of non-volatile data in the program memory. the application table section and boot sect ion can also be used for general application software. figure 7-1. flash program memory (hexadecimal address) word address 0 application section (256k/192k/128k/64k) ... 1efff / 16fff / efff / 77ff 1f000 / 17000 / f000 / 7800 application table section (8k/8k/8k/4k) 1ffff / 17fff / ffff / 7fff 20000 / 18000 / 10000 / 8000 boot section (8k/8k/8k/4k) 20fff / 18fff / 10fff / 87ff
11 8386a?avr?07/11 xmega a3u 7.4 data memory the data memory contains the i/o memory, internal sram, optionally memory mapped eeprom, and external memory if available. the data memory is organized as one continuous memory section, see figure 7-2 on page 11 . to simplify development, i/o memory, eeprom and sram will always have the same st art addresses for all xmega devices. figure 7-2. data memory map (hexadecimal address) byte address atxmega192a3u byte address atxmega128a3u byte address atxmega64a3u 0 i/o registers (4k) 0 i/o registers (4k) 0 i/o registers (4k) fff fff fff 1000 eeprom (2k) 1000 eeprom (2k) 1000 eeprom (2k) 17ff 17ff 17ff reserved reserved reserved 2000 internal sram (16k) 2000 internal sram (8k) 2000 internal sram (4k) 5fff 3fff 2fff byte address ATXMEGA256A3U 0 i/o registers (4k) fff 1000 eeprom (4k) 1fff 2000 internal sram (16k) 5fff
12 8386a?avr?07/11 xmega a3u 7.4.1 i/o memory the status and configuration registers for peripherals and modules, including the cpu, are addressable through i/o memory locations. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/st d) instructions, which is used to transfer data between the 32 registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range 0x00 - 0x3f directly. in the address range 0x00 - 0x1f, sin- gle- cycle instructions for manipulation and checking of individual bits are available. the i/o memory address for all peripherals and modules in xmega a3u is shown in the ?peripheral module address map? on page 56 . 7.4.2 sram data memory the devices have internal sram memory for data storage. 7.4.3 eeprom data memory the devices have inter nal eeprom memory for non-volatile data storage. it is addressable either in a separate data space or it c an be memory mapped into the normal data memory space. the eeprom memory supports both byte and page access.
13 8386a?avr?07/11 xmega a3u 7.5 production signature row the production signature row is a separate memory section for factory programmed data. it contains calibration data for functions such as oscillators and analog modules. the production signature row also contains an id that identifies each microcontroller device type, and a serial number that is unique for each manufactured device. the device id for the available devices is shown in table 7-1 on page 13 . the serial number consist of the production lot number, wafer number, and wafer coordinates for the device. the production signature row can not be written or erased, but it can be read from both applica- tion software and external programming. table 7-1. device id bytes for xmega a3u devices. 7.6 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programming. it is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identifica- tion numbers, random number seeds etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase session and on-chip debug sessions. device device id bytes byte 2 byte 1 byte 0 atxmega64a3u 42 96 1e atxmega128a3u 42 97 1e atxmega192a3u 44 97 1e ATXMEGA256A3U 42 98 1e
14 8386a?avr?07/11 xmega a3u 7.7 flash and eeprom page size the flash program memory and eeprom data memory are organize d in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 7-2 on page 14 shows the flash program memory organization. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the most significant bits in the address (fpage) gives the page number and the least significant address bits (fword) gives the word in the page. table 7-2. number of words and pages in the flash. table 7-3 on page 14 shows eeprom memory organizati on for the xmeg a a3u devices. eeeprom write and erase operatio ns can be perfo rmed one page or one by te at a time, while reading the eeprom is done one byte at a ti me. for eeprom access the nvm address regis- ter (addr[m:n]) is used for addre ssing. the most significant bits in the address (e2page) gives the page number and the least significant address bits (e2byte) gives the byte in the page. table 7-3. number of bytes and pages in the eeprom. devices flash page size fword fpage application boot size (words) size no of pages size no of pages atxmega64a3u 64k + 4k 128 z[7:1] z[16:8] 64k 256 4k 16 atxmega128a3u 128k + 8k 256 z[8:1] z[17:9] 128k 256 8k 16 atxmega192a3u 192k + 8k 256 z[8:1] z[18:9] 192k 384 8k 16 ATXMEGA256A3U 256k + 8k 256 z[8:1] z[18:9] 256k 512 8k 16 devices eeprom page size e2byte e2page no of pages size (bytes) atxmega64a3u 2k 32 addr[4:0] addr[10:5] 64 atxmega128a3u 2k 32 addr[4:0] addr[10:5] 64 atxmega192a3u 2k 32 addr[4:0] addr[10:5] 64 ATXMEGA256A3U 4k 32 addr[4:0] addr[11:5] 128
15 8386a?avr?07/11 xmega a3u 8. dmac - direct memory access controller 8.1 features ? the dma controller allows data tran sfers with minimal cpu intervention ? from data memory to data memory ? from data memory to peripheral ? from peripheral to data memory ? from peripheral to peripheral ? four dma channels with separate ? transfer triggers ? interrupt vectors ? addressing modes ? programmable channel priority ? from 1byte to 16mbytes of data in a single transaction ? multiple addressing modes ? static ?increment ? decrement ? optional reload of source and dest ination address at the end of each ?burst ?block ? transaction ? optional interrupt on end of transaction ? optional connection to crc genera tor module for crc on dma data 8.2 overview the 4-channel direct memory access (dma) controller can transfer data between memories and peripherals, and thus offload these tasks from the cpu. it enables high data transfer rates with minimum cpu intervention, and frees up cpu time. the 4 dma channels enable up to four independent and parallel transfers. the dma controller can move data between sram and peripherals, between sram locations and between peripheral registers directly. with access to all peripherals the dma controller can handle automatic transfer of data to/from communication modules, as well as data retrieval from adc conversions, or data transfer to or from por t pins. the dma controller can also read from memory mapped eeprom. data transfers are done in continues bursts of 1, 2, 4 or 8bytes. they build block transfers of configurable size from 1 to 64kbytes. a repeat counter can be used to repeat each block trans- fer for single transactions up to 16mbytes. source and destination addressing can be static, incremental or decremental. automatic reload of source and/or destination address can be done after each burst, block transfer, or when transaction is complete. application software, peripher- als and events can trigger dma transfers. the four dma channels have individual configurati on and control settings. this include source, destination, transfer triggers and transaction sizes. they have individual interrupt settings. inter- rupt requests can be generated both when a transaction is complete or if the dma controller detects an error on a dma channel. to allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa.
16 8386a?avr?07/11 xmega a3u 9. event system 9.1 features ? system for direct peripheral to pe ripheral communicat ion and signaling ? peripherals can directly send, recei ve and react to peripheral events ? cpu and dma controller independent operation ? 100% predictable signal timing ? short and guaranteed response time ? 8 event channels for up to 8 different and parallel sign al routines and configurations ? events can be sent and/or used by mo st peripherals, clock system and software ? additional functions include ? quadrature decoders ? digital filtering of i/o pin change ? works in active mode and idle sleep mode 9.2 overview the event system is system for direct peripheral to peripheral communication and signaling. it enables the possibility for a chang e in one peripheral to automatically trigger actions in others peripherals. it is designed for having a predi ctable system for short and guaranteed response time between peripherals. it is simple and powerful since it allows for autonomous peripheral control and interaction without use of interrupts, cpu or dma controller resources. it also enables synchronized timing of actions in several peripheral modules. the change in a peripheral is referred to as an event, and is it usually the same as the interrupt conditions for the peripheral. these events can be directly passed to other peripherals using a dedicated routing network called the event routing network. how events are routed and used by other peripherals is configured in software. figure 9-1 on page 17 shows a basic block diagram of all connected peripherals. the event system can directly connect together analog a nd digital converters, analog comparators, i/o ports pins, the real-time counter, timer/co unters, ir communication module (ircom), and usb. it can also be used to trigger dma transactions (dma controller). events can also be gen- erated from software and the peripheral clock.
17 8386a?avr?07/11 xmega a3u figure 9-1. event system block diagram. the event routing network consists of eight software configurable multiplexers that control how events are routed and used. this is called event channels and it enables up to eight parallel event configurations and routings. the maximum routing latency between two peripherals is two peripheral clock cycles. the event system works in both active mode and idle sleep mode. dac timer / counters usb adc real time counter port pins cpu / software dma controller ircom event routing network event system controller clk per prescaler ac
18 8386a?avr?07/11 xmega a3u 10. system clock and clock options 10.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32mhz run-time calibrate d and tuneable oscillator ? 2mhz run-time calib rated oscillator ? 32.768khz calibrated oscillator ? 32khz ultra low power (ulp) oscillator with 1khz output ? external clock options ? 0.4 - 16mhz cr ystal oscillator ? 32khz crystal oscillator ? external clock ? pll with 20 - 128mhz output frequency ? internal and external clock opti ons and 1 to 31x multiplication ? lock detector ? clock prescalers with 1 to 2048x division ? fast peripheral clocks running at 2 and 4 times the cpu clock frequency ? automatic run-time calibration of internal oscillators ? external oscillator and pll lock failure dete ction with optional non maskable interrupt 10.2 overview the flexible clock system supports a large number of clock sources. it in corporates both accu- rate internal oscillators, and exte rnal crystal oscillators and reso nator support. a high frequency phase locked loop (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic runtime calibration of the internal oscillators to re move frequency drift over voltage and temperate. an oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to inter- nal oscillator if the extern al oscillator or pll fails. when a reset occur, all clock sources except 32khz ultra low power os cillator are disabled. after reset, the device will alwa ys start up running from the 2mhz internal oscillator. during nor- mal operation, the system clock source and prescalers can be changed from software at any time. figure 10-1 on page 19 presents the principal clock system in the xmega. all of the clocks do not need to be active at a given time. the clocks to the cpu and peripherals can be stopped using sleep modes and power reduction registers.
19 8386a?avr?07/11 xmega a3u figure 10-1. the clock system, clock sources and clock distribution 10.3 clock options 10.3.1 32khz ultra low power internal oscillator this oscillator provides an ap proximate 32khz clock. the 32kh z ultra low powe r (ulp) internal oscillator is a very low power clock source, and it is not designed for high accuracy. the oscilla- tor employs a built in prescaler providing a 1khz output. the oscillator is automatically enabled/disabled when used as clock source for any part of the device. this oscillator can be selected as clock source for the rtc. 10.3.2 32.768khz calibrated internal oscillator this oscillator provides an approximate 32.768khz clock. a fa ctory-calibrated va lue is written to the 32.768khz oscillator ca libration register during reset to en sure that the osc illator is running- within its specification. the calibration register can also be written from software for run-time calibration of the oscillator freq uency. the oscillator employs a bu ilt in prescaler providing both a 32.768khz output and a 1.024khz output. real time counter peripherals ram avr cpu non-volatile memory watchdog timer brown-out detector system clock prescalers usb prescaler system clock multiplexer (sclksel) pllsrc rtcsrc div32 32 khz int. ulp 32.768 khz int. osc 32.768 khz tosc 2 mhz int. osc 32 mhz int. osc 0.4 ? 16 mhz xtal div32 div32 div4 xoscsel pll usbsrc tosc1 tosc2 xtal1 xtal2 clk sys clk rtc clk per2 clk per clk cpu clk per4 clk usb
20 8386a?avr?07/11 xmega a3u 10.3.3 32.768khz crystal oscillator a 32.768khz crystal oscillator ca n be connected between tosc1 and tosc2 pins and enable a dedicated low frequency oscillato r input circuit. a low power mode with reduced voltage swing on tosc2 is available. this osci llator can be used as clock source for the system clock, rtc and as the dfll reference clock. 10.3.4 0.4 - 16mhz crystal oscillator the 0.4 - 16mhz crystal oscillator is a driver intended for driving both external resonators and crystals ranging from 400khz to 16mhz. 10.3.5 2mhz run-time calibrated internal oscillator the 2mhz run-time calibra ted internal oscillator is the defaul t system clock source after reset. it is calibrated during production to provide a default frequency which is close to its nominal fre- quency. a digital frequency looked loop (dfll) that can be enabled for automatic run-time calibration of the oscilla tor to compensate for te mperature and voltage dri ft to optimize the oscil- lator accuracy. 10.3.6 32mhz run-time calibrated internal oscillator the 32mhz run-time calibrated inte rnal oscillator is a high freque ncy oscillator. it is calibrated during production to provide a default frequency which is close to its nominal frequency. a dfll that can be enabled for automatic run-time calibration of the osc illator to compensate for temper- ature and voltage drift to optimi ze the oscillator accuracy this oscillator can also be adjusted and calibrated to any frequency between 30 and 55mhz. 10.3.7 external clock input the external clock input gives the possibility to connect a cloc k from an external source to xtal1. 10.3.8 pll with multiplication factor 1 - 31x the pll provides the possibility of multiplying a frequency by any number from 1 to 31. in com- bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
21 8386a?avr?07/11 xmega a3u 11. power management and sleep modes 11.1 features ? power management for adjusting powe r consumption and enabled functions ? 5 sleep modes: ?idle ? power-down ?power-save ?standby ? extended standby ? power reduction register to disable clock and tu rn off unused peripherals in active and idle mode 11.2 overview various sleep modes and clock gating are implemented in order to tailor power consumption to the application's requirement. this enables the mi crocontroller to stop unused modules to save power. all sleep modes are available and can be entered from active mode. in active mode the cpu is executing application code. when the device enters sleep mode, program execution is stopped and interrupts or reset is used to wake the device again. the application code decides when and what sleep mode to enter. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. in addition, power reduction registers provide a method to stop the clock to individual peripher- als from software. when this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep mode and enable much more fine-tuned power management than sleep modes alone. 11.3 sleep modes 11.3.1 idle mode in idle mode the cpu and non-volatile memory are stopped, but all peripherals including the interrupt controller, event system and dma controller are kept running. any enabled interrupt will wake the device. 11.3.2 power-down mode in power-down mode all clocks, including the real time counter clock source are stopped. this only allows operation of asynchronous modules that does not require a running clock. the only interrupts that can wake up the mcu are the two wire interface address match interrupt, asyn- chronous port interrupts and usb resume interrupt. 11.3.3 power-save mode power-save mode is identical to power-down, wi th one exception, if the real time counter (rtc) is enabled, it will keep running during sl eep and the device can also wake up from either rtc overflow or compare match interrupt.
22 8386a?avr?07/11 xmega a3u 11.3.4 standby mode standby mode is identical to power-down with the exception that the enabled system clock sources are kept running, while the cpu, periph eral and rtc clocks are stopped. this reduces the wake-up time. 11.3.5 extended standby mode extended standby mode is identical to power-save mode with the exception that the enabled system clock sources are kept ru nning while the cpu and periph eral clocks are stopped. this reduces the wake-up time.
23 8386a?avr?07/11 xmega a3u 12. system control and reset 12.1 features ? reset the microcontroller and set it to its in itial state when a reset source goes active ? multiple reset sources that cover different situations ?power-on reset ? external reset ? watchdog reset ? brown-out reset ? pdi reset ? software reset ? asynchronous operation ? no running system clock in the device is required for the reset ? reset status register for reading the reset source from th e application code 12.2 overview the reset system issues a microcontroller reset and set the device to its initial state. this is for situation where operation should not start or continue, for example when the microcontroller operates below its power supply rating. if a reset source goes active, the device enters and be kept in reset until all reset sources have released their reset. the i/o pins are immediately tristated. the program counter is set to the reset vector location and all i/o registers are set to the initial value. the sram content is kept, but not guaranteed. after reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. by default this is the lowest pro- gram memory address, '0', but it is possible to move the reset vector to the lowest address in the boot section. the reset functionality is asynchronous, so no running system clock is required to reset the device. the software reset feature makes it possible to issue a controlled system reset from the user software. the reset status register has individual status flags for each reset source. it is cleared at power- on reset, it shows which sources that have issued a reset since the last power-on. 12.3 reset sources 12.3.1 power-on reset the device is reset when the supply voltage vcc is below the power-on reset threshold voltage. 12.3.2 external reset the device is reset when a low le vel is present on the reset pin. 12.3.3 watchdog reset the device is reset when the watchdog timer period expires and the watchdog reset is enabled. the watchdog timer runs from a dedicated oscillator independent of the system clock. for more details see ?wdt - watchdog timer? on page 25 .
24 8386a?avr?07/11 xmega a3u 12.3.4 brown-out reset the device is reset when the supply voltage vcc is below the brown-out reset threshold volt- age and the brown-out detector is enabled. the brown-out threshold voltage is programmable. 12.3.5 jtag reset the device is reset as long as there is a logic one in the reset register in one of the scan chains of the jtag system. refer to ieee 11 49.1 (jtag) boundary -scan for details. 12.3.6 pdi reset the mcu can be reset through the program and debug interface (pdi). 12.3.7 software reset the mcu can be reset by the cpu writing to a special i/o register through a timed sequence.
25 8386a?avr?07/11 xmega a3u 13. wdt - watchdog timer 13.1 features ? issues a device reset if the timer is not reset before its timeout period ? asynchronously operation from dedicated oscillator ? 1khz output of the 32khz ultra low power oscillator ? 11 selectable timeout periods, from 8ms to 8s. ? two operation modes ? normal mode ? window mode ? configuration lock to prevent unwanted changes 13.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situations such as run-away or dead-lock code. the wdt is a timer, configured to a predefined timeout period and is constantly running when enabled. if the wdt is not reset within the timeout period, it will issue a microcontroller reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the window mode makes it possible to define a time slot window inside the total timeout period where wdt must be reset within. if the wdt is re set too early or too late and outside this win- dow, a system reset will be issu ed. compared to the normal mode, this can also catch situations where a code error also caus es constant wdr execution. the wdt will run in active mode and all sleep modes if enabled. it is asynchronous and runs from a cpu independent clock source, and will cont inue to operate to issue a system reset even if the main clocks fail. the configuration c hange protection mechanism ensures that the wdt settings cannot be changed by accident. for increased safety, a fuse for locking the wdt set- tings is available.
26 8386a?avr?07/11 xmega a3u 14. interrupts and programmable mu lti-level interrupt controller 14.1 features ? short and predictable interrupt response time ? separate interrupt configuration and vector address for each interrupt ? programmable multi-level interrupt controller ? interrupt prioritizing according to level and vector address ? 3 selectable interrupt levels for all interrupts: low, medium and high ? selectable round-robin priority scheme within low level interrupts ? non-maskable interrupts for critical functions ? interrupt vectors can be moved from the app lication section to the boot loader section 14.2 overview atmel ? avr ? xmega ? have a programmable multi-level in terrupt controller (pmic). interrupts signal a change of state in peripherals, and this can be used to alter program execution. periph- erals can have one or more interrupts, and all are individually enabled and configured. when an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condi- tion is present. the programmable multi-level interrupt controller (pmic) controls the handling and prioritizing of interrupt requests. when an interrupt request is acknowledged by the pmic, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority levels for thei r interrupts; low, medium and high. interrupts are prioritized according to their level and their interrupt vector address. medium level interrupts will interrupt low level interrupt handlers. high level interrupts will inter- rupt both medium and low level interrupt handlers. within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. low level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) is also supported and can be used for critical functions. if a boot- loader is used, it is possible to move the interrupt vectors from the application section to the boot loader sections so interrupts can be used and executed also during self-programming. 14.3 interrupt vectors the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the xmega a3u devices are shown in table 14-1 . offset addresses for each interrupt available in the peripheral are described for each peripheral in the xmega au manual. for peripherals or modules that have only one interrupt, the interrupt vector is shown in table 14-1 . the program address is the word address. table 14-1. reset and interrupt vectors program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillato r failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base
27 8386a?avr?07/11 xmega a3u 0x008 portr_int_base port r interrupt base 0x00c dma_int_base dma controller interrupt base 0x014 rtc_int_base real time counter interrupt base 0x018 twic_int_base two-wire interface on port c interrupt base 0x01c tcc0_int_base timer/counter 0 on port c interrupt base 0x028 tcc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x03d usartc1_int_base usart 1 on port c interrupt base 0x03e aes_int_vect aes interrupt vector 0x040 nvm_int_base non-volatile memory interrupt base 0x044 portb_int_base port b interrupt base 0x048 acb_int_base analog comparator on port b interrupt base 0x04e adcb_int_base analog to digital converter on port b interrupt base 0x056 porte_int_base port e int base 0x05a twie_int_base two-wire interface on port e interrupt base 0x05e tce0_int_base timer/counter 0 on port e interrupt base 0x06a tce1_int_base timer/counter 1 on port e interrupt base 0x072 spie_int_vect spi on port e interrupt vector 0x074 usarte0_int_base usart 0 on port e interrupt base 0x07a usarte1_int_base usart 1 on port e interrupt base 0x080 portd_int_base port d interrupt base 0x084 porta_int_base port a interrupt base 0x088 aca_int_base analog comparator on port a interrupt base 0x08e adca_int_base analog to digital converter on port a interrupt base 0x09a tcd0_int_base timer/counter 0 on port d interrupt base 0x0a6 tcd1_int_base timer/counter 1 on port d interrupt base 0x0ae spid_int_vector spi d interrupt vector 0x0b0 usartd0_int_base usart 0 on port d interrupt base 0x0b6 usartd1_int_base usart 1 on port d interrupt base 0x0d0 portf_int_base port f interrupt base 0x0d8 tcf0_int_base timer/counter 0 on port f interrupt base 0x0ee usartf0_int_base usart 0 on port f interrupt base 0x0fa usb_int_base usb on port d interrupt base table 14-1. reset and interrupt vectors (continued) program address (base address) source interrupt description
28 8386a?avr?07/11 xmega a3u 15. i/o ports 15.1 features ? general purpose input and output pins with several and individual configuration options ? output driver with configurable driver and pull settings: ? totem-pole ? wired-and ?wired-or ? bus-keeper ? inverted i/o ? input with synchronous and/or asynchronous sensing with port interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? optimal pull-up and pull-down resistor on input and wired- or/and configurations ? optional slew rate control ? asynchronous pin change sensing that ca n wake-up the device from all sleep modes ? two port interrupts with pin masking per i/o port ? efficient and safe access to port pins ? hardware read-modify-write through dedicated togg le/clear/set registers ? configuration of multiple pins in a single operation ? mapping of port registers in to bit-accessible i/o memory space ? peripheral clocks output on port pin ? real time counter clock output to port pin ? event channel output on port pin ? remap of digital peripheral pin functions ? selectable usart, spi and timer/counter input/output pin locations 15.2 overview one port consists of up to 8 pins ranging from pin 0 to 7. each port pin can be configured as input or output with configurable driver and pull settings. they also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes wh ere no clocks are running. all functions are individual and configurable per pin, but several pins can be configured in one single operation. the pins have hardware read-modify-write (rmw) functionality for safe and correct change of drive value and/or pull resistor configuration. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the port pin configuration also controls input and output selection of other device function. it is possible to have both the peripheral clock and the real time clock output to a port pin, and avail- able for external use. the same applies to events from the event system that can be used to synchronize and control external functions. other digital peripherals such as usart, spi and timer/counters can be remapped to selectable pin location in order to optimize pinout versus application needs.
29 8386a?avr?07/11 xmega a3u 15.3 output driver all port pins (pn) have programmable output configuration. the port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 push-pull figure 15-1. i/o configuration - totem-pole 15.3.2 pull-down figure 15-2. i/o configuration - totem-pole with pull-down (on input) 15.3.3 pull-up figure 15-3. i/o configuration - totem-pole with pull-up (on input) inn outn dirn pn inn outn dirn pn inn outn dirn pn
30 8386a?avr?07/11 xmega a3u 15.3.4 bus-keeper the bus-keeper?s weak output produces the same logi cal level as the last output level. it acts as a pull-up if the last leve l was ?1?, and pull-down if the last level was ?0?. figure 15-4. i/o configuration - totem-pole with bus-keeper 15.3.5 others figure 15-5. output configuration - wired-or with optional pull-down figure 15-6. i/o configuration - wired-and with optional pull-up inn outn dirn pn inn outn pn inn outn pn
31 8386a?avr?07/11 xmega a3u 15.4 input sensing input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 15-7 on page 31 . figure 15-7. input sensing system overview when a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 15.5 alternate port functions in addition to the input/output functions on all po rt pins, most pins have alternate functions. this means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. ?pinout and pin functions? on page 51 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
32 8386a?avr?07/11 xmega a3u 16. t/c - 16-bit timer/counter 16.1 features ? seven 16-bit timer/counters ? four timer/counters of type 0 ? three timer/counters of type 1 ? 32-bit timer/counter support by cascading two timer/counters ? up to 4 compare or capture (cc) channels ? 4 cc channels for timer/counters of type 0 ? 2 cc channels for timer/counters of type 1 ? double buffered timer period setting ? double buffered captur e or compare channels ? waveform generation: ? frequency generation ? single slope pulse width modulation ? dual slope pulse width modulation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? timer overflow and error interrupts / events ? one compare match or input captur e interrupt / event per cc channel ? can be used with event system for ? quadrature decoding ? count and direction control ?capture ? can be used with dma and trigger dma transactions ? high-resolution extension ? increases frequency and waveform reso lution by 4x (2-bit), or 8x (3-bit) ? advanced waveform extension ? low and high-side output with prog rammable dead-time insertion (dti) ? event controlled fault protection for safe disabling of external drivers 16.2 overview there are seven flexible 16-bit timer/counters (t c). their capabilities in clude accurate program execution timing, frequency and waveform generation, and input capture with time and fre- quency measurement of digital signals. two time r/counters can be cascaded to create 32-bit timer/counter with optional 32-bit capture. a timer/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period setting that can be used for timing. th e cc channels can be used together with the base counter to do compare match control, frequency generation and pulse width waveform modula- tion, or various input capture operations. a timer/counter can be configured for either capture or compare functions, and not perform both at the same time.
33 8386a?avr?07/11 xmega a3u a timer/counter can be clocked and timed from the peripheral clock with optional prescaling or the event system. the event system can also be used for direction control, capture trigger or to synchronize operations. figure 16-1. overview of a timer/counter and closely related peripherals figure 16-2. overview of a timer/counter and closely related peripherals the only difference between timer/counter ty pe 0 and 1 is the number of cc channels. timer/counter 0 has four cc channels, and timer/counter 1 has two cc channels. all informa- tion related to cc channel 3 and 4 is only valid for timer/counter 0. the high resolution (hi-res) exte nsion can be used to increase the waveform output resolution by up to eight times, by using internal clock source running up to four times faster than the peripheral clock. see ?hi-res - high resolution extension? on page 35 for more details. the advanced waveform extension can be enabl ed to provide extra and more advanced fea- tures for the timer/counter. this are only available for timer/counter 0. see ?awex - advanced waveform extension? on page 34 for more details. portc, portd and porte each has one timer/counter 0 and one timer/counter1. portf has one timer/counter 0. notation of these are tcc0 (time/counter c0), tcc1, tcd0, tcd1, tce0, tce1 and tcf0, respectively. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dead-time insertion pattern generation clk per4 port event system clk per timer/counter
34 8386a?avr?07/11 xmega a3u 17. awex - advanced waveform extension 17.1 features ? wafeform output with complementary output from each compare channel ? 4 dead-time insertion (dti) units ? 8-bit resolution ? separate high and low side dead-time setting ? double buffered dead-time ? optionally halts timer du ring dead-time insertion ? pattern generation unit creating synchr onised bit pattern across the port pins ? double buffered pattern generation ? optionally distribution of one compare channel output across the port pins ? event controlled fault protection for instant and predictably fault triggering 17.2 overview the advanced waveform extension (awex) provides extra functions to the timer/counter in waveform generation (wg) modes. it is primaril y intended for different types of motor control and other power control applications. it enabl es low- and high side output with dead time insertion, and fault protection for disabling and s hutdown of drivers. it can also generate a syn- chronized bit pattern across the port pins. each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any awex features are enabled. these output pairs go through a dead- time insertion (dti) unit that generates the non-inverted low side (ls) and inverted high side (hs) of the wg output with dead time insertion between ls and hs switching. the dti output will override the normal port value acco rding to the port override setting. the pattern generation unit can be used to generate a synchronized bit pattern across the port it is connected to. in addition, the wg output from the compare channel a can be distributed to and override all the port pins. when the pattern generator unit is enabled the dti unit is bypassed. the fault protection unit is connected to the even t system, enabling any event to trigger a fault condition that will disable the aw ex output. the event system ensure predictable and instant fault reaction, and gives great flexibilit y in the selection of fault triggers. the awex is available for tcc0. the notation of this is awexc.
35 8386a?avr?07/11 xmega a3u 18. hi-res - high r esolution extension 18.1 features ? increases waveform generator resolu tion by up to 8 times (3-bit) ? supports frequency, single slope pwm and dual slope pwm generation ? supports the awex when this is used for the same timer/counter 18.2 overview the hi-resolution (hi-res) extension is able to increase the resolution of the waveform genera- tion output by a factor of four or eight. it can be used for a timer/counter doing frequency, single slope pwm or dual slope pwm generation. it can also be used with the awex if this is used for the same timer/counter. atmel ? avr ? xmega ? a3u devices have four hi-res exte nsions that each can be enabled for each timer/counters pair on portc, portd, porte and portf. the notation of these are hiresc, hiresd, hirese and hiresf, respectively.
36 8386a?avr?07/11 xmega a3u 19. rtc - 16-bit real-time counter 19.1 features ? 16-bit resolution ? selectable clock source ? 32.768khz external crystal ? external clock ? 32.768khz internal oscillator ? 32khz internal ulp oscillator ? programmable 10-bit clock prescaling ? one compare register ? one period register ? clear counter on period overflow ? optional interrupt/ event on overflow and compare match 19.2 overview the 16-bit real time counter (rtc) is a counter that typically runs continuously, including in low power sleep modes, to keep track of time. it can wake up the device from sleep modes and/or interrupt the device at regular intervals. the reference clock is typically the 1.024khz output from a high accuracy crystal of 32.768khz, and this is the configuration most optimized for low power consumption. the faster 32.768khz output can be selected if the rtc needs a higher resolution than 1ms. the rtc can also be clocked from an external clock signal, the inter nal 32.768khz oscillator or the internal 32khz ulp oscillator. the rtc includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. a wide range of resolution and time-out periods can be config- ured. with a 32.768khz clock source the maximum resolution of 30.5s, time-out periods range up to 2000seconds. with a resolution of 1 seco nd, the maximum time-out period is over 18hours (65536seconds). the rtc can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/event when it equals the period regis- ter value. figure 19-1. real-time counter overview 32.768khz crystal osc 32.768khz int. osc tosc1 tosc2 external clock div32 div32 32khz int ulp (div32) rtcsrc 10-bit prescaler clk rtc cnt per comp = = ?match?/ compare top/ overflow
37 8386a?avr?07/11 xmega a3u 20. usb - universal serial bus interface 20.1 features ? one usb 2.0 full speed (12m bps) and low speed (1.5mbps) device compliant interface ? integrated on-chip usb transceiver , no external components needed ? 16 endpoint addresses with full endpoint flexibility for up to 32 endpoints ? one input endpoint per endpoint address ? one output endpoint per endpoint address ? endpoint address transfer type selectable to ? control transfers ? interrupt transfers ? bulk transfers ? isochronous transfers ? configurable data payload size per endpoint, up to 1023bytes ? endpoint configuration and data buffers located in internal sram ? configurable location for endpoint configuration data ? configurable location for each endpoint's data buffer ? built in direct memory access (dma) to internal sram for ? endpoint configurations ? read and write of endpoint data ? ping-pong operation for higher throughput and double buffered operation ? input and output endpoint data buffers used in a single direction ? cpu/dma controller can update data buffer during transfer ? multi-packet transfer for reduced in terrupt load and software intervention ? data payload exceeding max packet size is transferred in one continuous transfer ? no interrupts or software interact ion on packet transaction level ? transaction complete fifo for easy flow ma nagement when using multiple endpoints ? tracks all completed transactions in a first come, first serve work-queue ? clock selection independent of system clock source selection ? connection to event system ? on chip debug possibilities during usb transactions 20.2 overview the usb interface is an usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compli- ant interface. it supports 16 endpoint addresses. all endpoint addresses have one input and one output end- point, for a total of 32 endpoints. each endpoint address is fully configurable and can be configured for any of the four transfer types: control, interrupt, bulk or isochronous. the data payload size is also selectable and it supports data payloads up to 1023bytes. no dedicated memory is allocate d for or included in the usb mo dule. internal sram is used to keep the configuration for each endpoint address, and the data buffer for each endpoint. the memory locations used for endpoint configurations and data buffers are fully configurable. the amount of memory allocated is fully dynamic according to the number of endpoints in use, and the configuration of these. the usb module has built-in direct memory access (dma) and will read/write data from/to the sram when a usb transaction takes place. to maximise throughput, an endpoint address can be configured for ping-pong operation. when this is done, the input and output endpoints are both used in the same direction. the cpu or
38 8386a?avr?07/11 xmega a3u dma controller can then read/write one data buffer while the usb module writes/reads the other, and vice versa. this gives double buffered communication. multi-packet transfer enables a data payload ex ceeding the maximum packet size of an end- pointto be transferred as multiple packets without software intervention. this reduce the cpu intervention and the interrupts needed for usb transfers. for low power operation, the usb module can put the microcontroller in any sleep mode when the usb bus is idle and a suspend condition is given. upon bus resume, the usb module can wake the microcontroller from any sleep mode. portd has one usb. notation of this is usbd.
39 8386a?avr?07/11 xmega a3u 21. twi - two wire interface 21.1 features ? two identical two wire interface peripherals ? bi-directional tw o-wire communication interface ? phillips i 2 c compatible ? system management bus (smbus) compatible ? bus master and slave operation supported ? slave operation ? single bus master operation ? bus master in multi-master bus environment ? multi-master arbitration ? flexible slave address match functions ? 7-bit and general call address recognition in hardware ? 10-bit addressing supported ? address mask register for dual a ddress match or address range masking ? optional software address recognitio n for unlimited number of addresses ? slave can operate in all sleep modes ? slave address match can wake device from all sleep modes ? 100khz and 400khz bus frequency support ? slew-rate limited output drivers ? input filter for bus noise and spike suppression ? support arbitration between start/re peated start and data bit (smbus) ? slave arbitration allows support for ad dress resolve protocol (arp) (smbus) 21.2 overview the two wire interface is a bi-directional two-wire communication interface. it is i 2 c and system management bus (smbus) compatible. the only external hardware needed to implement the bus is one pull-up resistor on each bus line. the twi module supports master and slave functionality. the master and slave functionality are separated from each other and can be enabled and configured separately. the master module supports multi-master bus operation and arbitration. it contains the baud rate generator. both 100khz and 400khz bus frequency is supported. the slave module implements 7-bit address match and general address call recognition in hard- ware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a register for address range masking. the slave continues to operate in all sleep modes, including power down mode. this enables the slave to wake up the device from all sleep modes on twi address match. it is possible to disable the address matching to let this be handled in software instead. smart mode can be enabled to auto trigger operations and reduce software complexity. the twi module will detect start and stop c onditions, bus collision and bus errors. arbitra- tion lost, errors, collision and clock hold on the bus is also detected and indicated in separate status flags available in both master and slave mode. it is possible to disable the twi drivers in the device, and enable a 4-wire digital interface for connecting to an external twi bus driver. this can be used for applications where the device operates from a different vcc voltage than used by the twi bus. portc and porte each has one twi. notation of these peripherals are twic and twie.
40 8386a?avr?07/11 xmega a3u 22. spi - serial peripheral interface 22.1 features ? three identical spi peripherals ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? interrupt flag at the end of transmission ? write collision flag to indicate data collision ? wake-up from idle mode ? double speed master mode 22.2 overview the serial peripheral interfac e (spi) is a high-speed synchronous data transfer interface using three or four pins. it allows fast co mmunication between an xmega device and peripheral devices or other microcontrollers. the spi supports full duplex communication. a device connected to the bus must act as a master or slave. the master initiates and controls all data transactions, and data is transferred both to and from the device simultaneously. portc, portd, and porte each has one spi. notation of these peripherals are spic, spid, and spie respectively.
41 8386a?avr?07/11 xmega a3u 23. usart 23.1 features ? seven identical usart peripherals ? full duplex operation ? asynchronous or synchronous operation ? synchronous clock rates up to 1/2 o the device clock frequency ? asynchronous clock rates up to 1/8 of the device clock frequency ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? fractional baud rate generator ? can generate desired baud rate from any system clock frequency ? no need for external oscill ator with certain frequencies ? built in error detectio n and correction schemes ? odd or even parity gene ration and parity check ? data over run and fr aming error detection ? noise filtering includes false start bit detection and digital low pass filter ? separate interrupts for ? transmit complete ? transmit data register empty ? receive complete ? multi-processor communication mode ? addressing scheme to address a specific devices on a multi-device bus ? enable unaddressed devices to automatically ignore all frames ? master spi mode ? double buffered operation ? configurable data order ? high speed operation up to 1/2 of the peripheral clock frequency ? ircom module for irda compliant pulse modulation/demodulation 23.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a fast and flexible serial communication module. the usart supports full duplex communication, and both asynchronous and clocked synchronous operation. the usart can also be set in master spi mode and be used for spi communication. communication is frame based, and the frame format can be customized to support a wide range of standards. the usart is buffered in both direction, enabling continued data transmis- sion without any delay between frames. there are separate interrupts for receive and transmit complete, enabling fully interrupt driven communication. frame error and buffer overflow are detected in hardware and indicated with separate status flags. even or odd parity generation and parity check can also be enabled. the clock generation logic has a fractional baud rate generator that is able to generate a wide range of usart baud ra tes from any system clock frequenc ies. this remove the need to use an external crystal oscillator wit h a certain frequency in order to achieve a required baud rate. it also includes support external clock input in synchronous slave operation. one usart can use the ircom module to suppor t irda 1.4 physical compliant pulse modula- tion and demodulation for baud rates up to 115.2kbps. portc, portd, and porte each has two usarts, while portf has one usart only. notation of these peripherals are usartc0, usartc1, usartd0, usartd1, usarte0, usarte1 and usartf0, respectively.
42 8386a?avr?07/11 xmega a3u 24. ircom - ir communication module 24.1 features ? pulse modulation/demodulation for infrared communication ? irda compatible for baud rates up to 115.2kbps ? selectable pulse modulation scheme ? 3/16 of baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built in filtering ? can be connected to and used by one usart at a time 24.2 overview the infrared communication module (ircom) is used for irda communication with baud rates up to 115.2kbps. there is one ircom available which can be connected to any usart to enable infrared pulse coding/decoding for that usart.
43 8386a?avr?07/11 xmega a3u 25. aes and des crypto engine 25.1 features ? data encryption standard (des) cpu instruction ? advanced encryption stan dard (aes) crypto module ? des instruction ? encryption and decryption ? single-cycle des instruction ? encryption/decryption in 16 clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? support 128-bit keys ? support xor data load mode to the state memory for cipher block chaining ? encryption/decryption in 375 clock cycles per 16-byte block 25.2 overview the advanced encrypti on standard (aes) and da ta encryption standar d (des) are two com- monly used standards for cryptography. these are sup ported through an aes peripheral module and a des cpu instruction, and the communication interfaces and the cpu can use these for fast encrypted communication and secure data storage. des is supported by an instruction in the avr cp u. the 8-byte key and 8-byte data blocks must be loaded into the register file, and then the des instruction must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. the key and data must be loaded into the key and state memory in the module before encryp- tion/ decryption is started. it takes 375 peripher al clock cycles before the encryption/decryption is done. the encrypted/encrypted data can then be read out, and an optional interrupt can be generated. the aes crypto module also has dma support with transfer triggers when encryp- tion/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
44 8386a?avr?07/11 xmega a3u 26. crc - cyclic redundancy check generator 26.1 features ? cyclic redundancy check (crc) generation and checking for ? communication data ? program or data in flash memory ? data in sram memory and i/o memory space ? integrated with flash memory, dma controller and cpu ? continuous crc on data going through a dma channel ? automatic crc of the complete, or selectable range of the flash memory ? cpu can load data to crc ge nerator through i/o interface ? crc polynomial software selectable to ? crc-16 (crc-ccitt) ? crc-32 (ieee 802.3) ? zero remainder detection 26.2 overview a cyclic redundancy check (crc) is a test algori thm used to detect accidental errors on data, and is commonly used to determine the correctness of a data transmission, data memory and program memory. a crc takes a data stream or block of data as input and generates a 16- or 32-bit output that can be kept with the data and used as checksum. when the same data is later received or read, the device or application repeats the calculation. if the new crc calculation does not match the one calculated earlier, th e block contains a data error. the application will then detect this and may take corrective action such as requesting the data to be sent again. typically, an n-bit crc, applied to a data block of arbitrary length, will detect any single error burst not longer than n bits (in other words, any single alteration that spans no more than n bits of the data), and will detect a fraction 1-2 -n of all longer error bursts.the crc module in xmega supports two commonly used crc polyno mials; crc-16 (crc-ccitt) and crc-32 (ieee 802.3). ? crc-16: ? crc-32: polynomial: x 16 + x 12 + x 5 +1 hex value: 0x1021 polynomial: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 hex value: 0x04c11db7
45 8386a?avr?07/11 xmega a3u 27. adc - 12-bit analog to digital converter 27.1 features ? two analog to digital converters ? 12-bit resolution ? up to 2 million samples per second ? 4 inputs can be sampled within 1.5s ? down to 2.5s conversion time with 8-bit resolution ? down to 3.5s conversion ti me with 12-bit resolution ? differential and single-ended input ? up to 16 single-ended inputs ? 16x4 differential inputs without gain ? 16x4 differential input with gain ? built in differential gain stage ? 1/2 x, 1x, 2x, 4x, 8x, 16x, 32x and 64x gain options ? single, continues and sc an conversion options ? 4 internal inputs ? internal temperature sensor ? dac output ? vcc voltage divided by 10 ? 1.1v bandgap voltage ? 4 conversion channels wi th individual input cont rol and result registers ? enable 4 parallel configurations and results ? internal and external reference options ? compare function for accurate monito ring of user defined thresholds ? optional event triggered co nversion for accurate timing ? optional dma transfer of conversion results ? optional interrupt/even t on compare result 27.2 overview there are two analog to digital converters (adcs) modules that can be operated simultane- ously, individually or synchronized. the adc converts analog signals to digital values . the adc has 12-bit resolution and is capable of converting up to 2million sa mples per second (msps). the inpu t selection is flexible, and both single-ended and differential measurements can be done. for differential measurements an optional gain stage is available to increase the dynamic range. in addition several internal signal inputs are available. the adc can provide both signed and unsigned results. this is a pipelined adc that consists of several consecutive stages. the pipelined design allows high sample rate at a low system clock frequency. it also means that a new input can be sam- pled and a new adc conversion started while other adc conversions are still ongoing. this remove dependencies between sample rate and propagation delay. the adc has four conversion channels (channel 0-3) with individual input selection, result reg- isters and conversion start control. the adc can then keep and use four parallel configurations and results, and this will ease use for applications with high data throughput or multiple modules using the adc independently. it is possible to us e dma to move adc results directly to memory or peripherals when conversions are done. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the output from the dac, vcc/10 and the bandgap voltage can also be measured by the adc.
46 8386a?avr?07/11 xmega a3u the adc has a compare function for accurate monitoring of user defined thresholds with mini- mum software intervention required. figure 27-1. adc overview four inputs can be sampled within 1.5s without any intervention by the application. the adc may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) from 3.5s for 12-bit to 2.5s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). porta and portb each has one adc. notation of these peripherals are adca and adcb, respectively. adc ch1 result ch0 result ch2 result compare register < > ?x - 64x threshold (int req) internal 1.00v internal vcc/1.6v arefa arefb v inp v inn internal signals internal vcc/2 internal signals ch3 result adc0 adc15 adc4 adc7 ? ? ? ? ? ? adc0 adc3 ? ? ? int. signals int. signals reference voltage
47 8386a?avr?07/11 xmega a3u 28. dac - 12-bit digital to analog converter 28.1 features ? one digital to analog converter (dac) ? 12-bit resolution ? up to 1million samples per second conversion rate per dac channel ? built in calibration that removes ? offset error ? gain error ? multiple conversion trigger sources ? on new available data ? events from the event system ? high drive capabili ties and support for ? resistive load ? capacitive load ? combined resistive and capacitive load ? internal and external reference options ? dac output available as input to analog comparator and adc ? low power mode with reduced drive strength ? optional dma transfer of data 28.2 overview the digital to analog converter (dac) converts digita l values to voltages. each dac has two channels, 12-bit resolution, and is capable of c onverting 1million samples per second (msps) on each channels. the built-in calibration system can remove offset and gain error when loaded with calibration values from software. figure 28-1. dac overview a dac conversion is automatically started when new data to be converted is available. event from the event system can also be used, and this enable synchronized and timed conversions between the dac and other peripherals such as a timer/counter. the dma controller can be used to transfer data to the dac. the dac has high drive strengths and is capable of driving both resistive and capacitive loads, and a load which is a combination of this. a low power mode is av ailable, and this will reduce the drive strengths of the output. both internal and external voltage reference can be used. the dac output is also internally available for use as input to the analog comparator or adc. portb each has one dac. notation of this peripheral is dacb. dac0 dac1 ctrla ch1data ch0data trigger trigger internal output enable enable internal 1.00v arefa arefb reference selection avcc output driver output driver d a t a int. driver d a t a ctrlb dma req (data empty) dma req (data empty) select 12 12 select enable to ac/adc
48 8386a?avr?07/11 xmega a3u 29. ac - analog comparator 29.1 features ? four analog comparators ? selectable propagation delay vs current consumption ? selectable hysteresis ?no ?small ?large ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? output from the dac ? bandgap reference voltage. ? a 64-level programmable voltage scaler of the internal vcc voltage ? interrupt and event generation on ? rising edge ? falling edge ?toggle ? window function interrupt and event generation on ? signal above window ? signal inside window ? signal below window ? constant current source with configurable output pin selection 29.2 overview the analog comparator (ac) compares the voltage level on two inputs and gives a digital output based on this comparison. the analog comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. two important properties of the analog comparator when it comes to the dynamic behavior, are hysteresis and propagation delay. both these parameters may be adjusted in order to find the optimal operation for each application. the input section includes analog port pins, several internal signals and a 64-level programma- ble voltage scaler. the analog comparator output state can also be directly available on a pin for use by external devices. using as pair they ca n also be set in window mode to monitor a signal compared to a voltage window instead of a voltage level. a constant current source can be enabled, and output on a selectable pin. this can be used to replace for example external resistors used to charge capacitors in capacitive touch sensing applications. the analog comparators are always grouped in pairs on each port. they have identical behav- ior but separate control registers. porta and portb each has one ac pair. notations are aca and acb, respectively.
49 8386a?avr?07/11 xmega a3u figure 29-1. analog comparator overview the window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in figure 29-2 .. figure 29-2. analog comparator window function voltage scaler acnmuxctrl acnctrl interrupt mode enable enable hysteresis hysteresis dac bandgap ac1out winctrl interrupt sensititivity control & window function events interrupts ac0out pin input pin input pin input pin input ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
50 8386a?avr?07/11 xmega a3u 30. programming and debugging 30.1 features ? programming ? external programming through the pdi or jtag interface minimal protocol overhead for fast operation built in error detection and handling for reliable operation ? bootloader support for programming through any communication interface ? debugging ? non-intrusive real-tim e on-chip debug system ? no software or hardware resources required from device expect pin connection ? program flow control go, stop, reset, step into, step over, step out, run-to-cursor ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, break on: data location read, write or both read and write data location content equa l or not equal to a value data location content is greater or smaller than a value data location content is within or outside a range ? no limitation on device clock frequency ? program and debug interface (pdi) ? 2-pin interface for external programming and debugging ? uses the reset pin and a dedicated pin ? no i/o pins required during programming or debugging ? jtag interface ? 4-pin ieee std. 1149.1 co mpliant interface for pr ogramming and debugging ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard 30.2 overview atmel ? avr ? xmega ? devices together with atmel?s development tool chain include the neces- sary functions for efficient development. all external programming and debugging are done through the program and debug interface (pdi), or the jtag interface. the program and debug interface is 2-pin interface that uses the reset pin and a dedicated pin. no i/o pins are required during programming or debugging. the jtag interface is a 4-pin ieee std. 1149.1 compliant interface. this also has boundary- scan capabilities according to the ieee std. 1149.1 (jtag) standard in addition to the pdi and jtag interface, programming can also be done through a bootloader. a bootloader in the device can use any other communication interface such as uart, twi or spi to download and program new application code to the flash memory. debug is supported thro ugh a on-chip debug system that offe rs non-intrusive real-time debug. it does not require any software or hardware resources expect for the device expect pin connec- tion. using atmel?s tool chain, it offers complete program flow control and has supported for unlimited number of program and complex data breakpoints. application debug can be done from c and high level language source code level, as well as assembler and disassembler level.
51 8386a?avr?07/11 xmega a3u 31. pinout and pin functions the device pinout is shown in ?pinout/block diagram? on page 3 . in addition to general purpose i/o functionality, each pin can have several al ternate functions. this will depend on which peripheral is enabled and connected to the actual pin. only one of the pin functions can be used at time. 31.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 31.1.1 operation/power supply 31.1.2 port interrupt functions 31.1.3 analog functions 31.1.4 timer/counter and awex functions vcc digital supply voltage avcc analog supply voltage gnd ground sync port pin with full synchronous and limited asynchronous interrupt function async port pin with full syn chronous and full asynchro nous interrupt function acn analog comparator input pin n acnout analog comparator n output adcn analog to digital converter input pin n dacn digital to analog converter output pin n aref analog reference input pin ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n
52 8386a?avr?07/11 xmega a3u 31.1.5 communication functions 31.1.6 oscillators, clock and event 31.1.7 debug/system functions scl serial clock for twi sda serial data for twi sclin serial clock in for twi when external driver interface is enabled sclout serial clock out for twi when external driver interface is enabled sdain serial data in for twi when external driver interface is enabled sdaout serial data out for twi when ex ternal driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n s s slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi d- data- for usb d+ data+ for usb toscn timer oscillator pin n xtaln input/output for oscillator pin n clkout peripheral clock output evout event channel 0 output rtcout rtc clock source output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin t c k j tag te s t c l o c k tdi jtag test data in t d o j tag te s t d a t a o u t t m s j tag te s t m o d e s e l e c t
53 8386a?avr?07/11 xmega a3u 31.2 alternate pin functions the tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. the head row shows what peripheral that enable and use the alternate pin functions. for better flexibility, some alternate functions also have selectable pin locations for their func- tions, this is noted under the the first table where this apply. table 31-1. port a - alternate functions port a pin # interrupt adca pos/gainpos adcb pos/gainpos adca neg adca gainneg aca pos aca neg aca out refa gnd 60 avcc 61 pa0 62 sync adc0 adc8 adc0 ac0 ac0 aref pa1 63 sync adc1 adc9 adc1 ac1 ac1 pa2 64 sync/async adc2 adc10 adc2 ac2 pa3 1 sync adc3 adc11 adc3 ac3 ac3 pa4 1 sync adc4 adc12 adc4 ac4 pa5 1 sync adc5 adc13 adc5 ac5 ac5 pa6 4 sync adc6 adc14 adc6 ac6 ac1out pa7 5 sync adc7 adc15 adc7 ac7 ac0out table 31-2. port b - alternate functions port b pin # interrupt adca pos/gainpos adcb pos/gainpos adcb neg adcb gainneg acb pos acb neg acb out dacb refb jtag pb0 6 sync adc8 adc0 adc0 ac0 ac0 aref pb1 7 sync adc9 adc1 adc1 ac1 ac1 pb2 8 sync/async adc10 adc2 adc2 ac2 dac0 pb3 9 sync adc11 adc3 adc3 ac3 ac3 dac1 pb4 10 sync adc12 adc4 adc4 ac4 tms pb5 11 sync adc13 adc5 adc5 ac5 ac5 tdi pb6 12 sync adc14 adc6 adc6 ac6 ac1out tck pb7 13 sync adc15 adc7 adc7 ac7 ac0out tdo gnd 14 vcc 15
54 8386a?avr?07/11 xmega a3u notes: 1. pin mapping of all tc0 can optionally be moved to high nibble of port. 2. pin mapping of all usart0 can optionally be moved to high nibble of port. 3. pins mosi and sck for all spi can optionally be swapped. 4. clkout can optionally be moved between port c, d and e and between pin 4 and 7. 5. evout can optionally be moved between port c, d and e and between pin 4 and 7. table 31-3. port c - alternate functions port c pin # interrupt tcc0 (1) awexc tcc1 usartc0 (2) usartc1 spic (3) twic clockout (4) eventout (5) pc0 16 sync oc0a oc0als sda pc1 17 sync oc0b oc0ahs xck0 scl pc2 18 sync/async oc0c oc0bls rxd0 pc3 19 sync oc0d oc0bhs txd0 pc4 20 sync oc0cls oc1a ss pc5 21 sync oc0chs oc1b xck1 mosi pc6 22 sync oc0dls rxd1 miso rtcout pc7 23 sync oc0dhs txd1 sck clk per evout gnd 24 vcc 25 table 31-4. port d - alternate functions port d pin # interrupt tcd0 tcd1 usbd usartd0 usartd1 spid twid clockout eventout pd0 26 sync oc0a sda pd1 27 sync oc0b xck0 scl pd2 28 sync/async oc0c rxd0 pd3 29 sync oc0d txd0 pd4 30 sync oc1a ss pd5 31 sync oc1b xck1 mosi pd6 32 sync d- rxd1 miso pd7 33 sync d+ txd1 sck clk per evout gnd 33 vcc 34 table 31-5. port e - alternate functions port e pin # interrupt tce0 awexe tce1 us arte0 usarte1 spie twie clockout eventout pe0 36 sync oc0a oc0als sda pe1 37 sync oc0b oc0ahs xck0 scl pe2 38 sync/async oc0c oc0bls rxd0 pe3 39 sync oc0d oc0bhs txd0 pe4 40 sync oc0cls oc1a ss pe5 41 sync oc0chs oc1b xck1 mosi pe6 42 sync oc0dls rxd1 miso pe7 43 sync oc0dhs txd1 sck clk per evout gnd 44 vcc 45
55 8386a?avr?07/11 xmega a3u table 31-6. port f - alternate functions port f pin # interrupt tcf0 usartf0 pf0 46 sync oc0a pf1 47 sync oc0b xck0 pf2 48 sync/async oc0c rxd0 pf3 49 sync oc0d txd0 pf4 50 sync pf5 51 sync gnd 52 vcc 53 pf6 54 sync pf7 53 sync table 31-7. port r- alternate functions port r pin # interrupt pdi xtal pdi 56 pdi_data reset 57 pdi_clock pro 58 sync xtal2 pr1 59 sync xtal1
56 8386a?avr?07/11 xmega a3u 32. peripheral modu le address map the address maps show the base address for each peripheral and module in xmega a3u. for complete register description and summary for each peripheral module, refer to the xmega au manual. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 3 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32mhz internal oscillator 0x0068 dfllrc2m dfll for the 2mhz internal oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 wdt watch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00c0 aes aes module 0x00d0 crc crc module 0x0100 dma dma controller 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0240 adcb analog to digital converter on port b 0x0320 dacb digital to analog converter on port b 0x0380 aca analog comparator pair on port a 0x0390 acb analog comparator pair on port b 0x0400 rtc real time counter 0x0480 twic two wire interface on port c 0x04a0 twie two wire interface on port e 0x04c0 usb usb device 0x0600 porta port a 0x0620 portb port b 0x0640 portc port c 0x0660 portd port d 0x0680 porte port e 0x06a0 portf port f 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 awexc advanced waveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08b0 usartc1 usart 1 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0900 tcd0 timer/counter 0 on port d 0x0940 tcd1 timer/counter 1 on port d 0x0990 hiresd high resolution extension on port d 0x09a0 usartd0 usart 0 on port d 0x09b0 usartd1 usart 1 on port d 0x09c0 spid serial peripheral interface on port d 0x0a00 tce0 timer/counter 0 on port e 0x0a40 tce1 timer/counter 1 on port e 0x0a80 awexe advanced waveform extension on port e 0x0a90 hirese high resolution extension on port e 0x0aa0 usarte0 usart 0 on port e 0x0ab0 usarte1 usart 1 on port e 0x0ac0 spie serial peripheral interface on port e 0x0b00 tcf0 timer/counter 0 on port f
57 8386a?avr?07/11 xmega a3u 0x0b90 hiresf high resolution extension on port f 0x0ba0 usartf0 usart 0 on port f 0x0bc0 spif serial peripheral interface on port f base address name description
58 8386a?avr?07/11 xmega a3u 33. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff - rd z,c,n,v,s 1 neg rd two?s complement rd $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd - 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 mul rd,rr multiply unsigned r1:r0 rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) z, eind none 2 jmp k jump pc k none 3 rcall k relative call subroutine pc pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) z, eind none 3 (1)
59 8386a?avr?07/11 xmega a3u call k call subroutine pc k none 3 / 4 (1) ret subroutine return pc stack none 4 / 5 (1) reti interrupt return pc stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd rr none 1 movw rd, rr copy register pair rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 lds rd, k load direct from data space rd (k) none 2 (1)(2) ld rd, x load indirect rd (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x x - 1, rd (x) x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd (y) (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y (y) y + 1 none 1 (1)(2) mnemonics operands description operation flags #clocks
60 8386a?avr?07/11 xmega a3u ld rd, -y load indirect and pre-decrement y rd y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd (y + q) none 2 (1)(2) ld rd, z load indirect rd (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) rd none 2 (1) st x, rr store indirect (x) rr none 1 (1) st x+, rr store indirect and post-increment (x) x rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) x - 1, rr none 2 (1) st y, rr store indirect (y) rr none 1 (1) st y+, rr store indirect and post-increment (y) y rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) rr none 2 (1) st z, rr store indirect (z) rr none 1 (1) st z+, rr store indirect and post-increment (z) z rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) rr none 2 (1) lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-increment rd z (z), z + 1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z (rampz:z), z + 1 none 3 spm store program memory (rampz:z) r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z r1:r0, z + 2 none - in rd, a in from i/o location rd i/o(a) none 1 out a, rr out to i/o location i/o(a) rr none 1 push rr push register on stack stack rr none 1 (1) pop rd pop register from stack rd stack none 2 (1) xch z, rd exchange ram location temp rd (z) rd, (z), te m p none 2 las z, rd load and set ram location temp rd (z) rd, (z), te m p v ( z ) none 2 lac z, rd load and clear ram location (z) rd ($ff ? rd) ? (z) (z) none 2 mnemonics operands description operation flags #clocks
61 8386a?avr?07/11 xmega a3u notes: 1. cycle times for data memo ry accesses assume internal me mory accesses, and are not valid for accesses via the external ram interface. 2. one extra cycle must be added when accessing internal sram. lat z, rd load and toggle ram location (z) rd rd (z) (z) none 2 bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c rd(n+1), 0, rd(0) z,c,n,v 1 rol rd rotate left through carry rd(0) rd(n+1) c c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0sreg(s)1 sbi a, b set bit in i/o register i/o(a, b) 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) 0 none 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0h1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
62 8386a?avr?07/11 xmega a3u 34. packaging information 34.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
63 8386a?avr?07/11 xmega a3u 34.2 64m2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m2 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, e 64m2 2010-10-20 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 7.50 7.65 7.80 8.90 9.00 9.10 8.90 9.00 9.10 e e2 7.50 7.65 7.80 e 0.50 bsc l 0.35 0.40 0.45 top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 0.20 0.27 0.40 2. dimension and tolerance conform to asmey14.5m-1994. 0.20 ref a3 a3 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k notes: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 7.65 mm exposed pad, micro lead frame package (mlf)
64 8386a?avr?07/11 xmega a3u 35. electrical characteristics all typical values are measured at t = 25 c unless other temperature condition is given. all min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 35.1 absolute maximum ratings* 35.2 dc characteristics operating temperature.................................... -55 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground..-0.5v to v cc +0.5v maximum operating voltage ............................................ 4.0v dc current per i/o pin ................................................ 20.0ma dc current v cc and gnd pins................................. 200.0ma table 35-1. current consumption for active and sleep modes symbol parameter condition min typ max units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 148 a v cc = 3.0v 287 1mhz, ext. clk v cc = 1.8v 345 v cc = 3.0v 697 2mhz, ext. clk v cc = 1.8v 575 700 v cc = 3.0v 1.15 1.6 ma 32mhz, ext. clk 10.6 15 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 4.3 a v cc = 3.0v 4.8 1mhz, ext. clk v cc = 1.8v 78 v cc = 3.0v 147 2mhz, ext. clk v cc = 1.8v 156 250 v cc = 3.0v 293 600 32mhz, ext. clk 4.7 7.0 ma i cc power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t = 85c 1.75 5.0 wdt and sampled bod enabled, t=25c v cc = 3.0v 1.3 3.0 wdt and sampled bod enabled, t=85c 3.1 7.0
65 8386a?avr?07/11 xmega a3u notes: 1. all power reduction registers set. 2. maximum limits are based on characterization and not tested in production. i cc power-save power consumption (2) rtc on ulp clock, wdt and sampled bod enabled, t = 25c a v cc = 3.0v 1.3 rtc on 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.5 2 v cc = 3.0v 0.7 2 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 0.9 3 v cc = 3.0v 1.15 3 reset power consumption current through reset pin substracted v cc = 3.0v 1150 module and peripheral power consumption (3) i cc ulp oscillator a 32.768khz int. oscillator 27 2mhz int. oscillator 85 dfll enabled with 32.768khz int. osc. as reference 115 32mhz int. oscillator 270 dfll enabled with 32.768khz int. osc. as reference 460 pll multiplication factor = 20x 220 real time counter 0.015 watchdog timer 1 bod continuous mode 138 sampled mode, include ulp oscillator 1.2 internal 1.0v reference 100 temperature sensor 95 adc 250 ksps vref = ext ref 3.0 ma currlimit = low 2.61 currlimit = medium 2.16 currlimit = high 1.06 dac 250ksps vref = ext ref no load normal mode 1.63 low power mode 1.06 ac high speed mode 330 a low power mode 130 dma 615kbps between i/o registers and sram 115 timer/counter 16 usart rx and tx enabled, 9600 baud 2.5 flash memory and eeprom programming 4 ma table 35-1. current consumption for active and sleep modes (continued) symbol parameter condition min typ max units
66 8386a?avr?07/11 xmega a3u 3. all parameters measured as the difference in current co nsumption between module enabled and disabled. all data at v cc =3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditiond are given . 35.3 operating volt age and frequency the maximum system clock frequency of the atmel ? avr ? xmega a3u devices is depending on v cc . as shown in figure 35-1 on page 66 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 35-1. maximum frequency vs. vcc table 35-2. operating voltage and frequency symbol parameter condition min typ max units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32 1. 8 12 32 mhz v 2.7 3.6 1.6 safe operating area
67 8386a?avr?07/11 xmega a3u 35.4 wakeup time from sleep table 35-3. device wakeup time from sleep mode s with various system clock sources symbol parameter condition min typ max units t wakeup wake-up time from idle external 2mhz clock 2 s 32.768khz internal oscillator 120 2mhz internal oscillator 2 32mhz internal oscillator 0.2 wake-up time from standby external 2mhz clock 2 32.768khz internal oscillator 120 2mhz internal oscillator 2 32mhz internal oscillator 0.2 wake-up time from extend standby external 2mhz clock 2 32.768khz internal oscillator 120 2mhz internal oscillator 2 32mhz internal oscillator 0.2 wake-up time from power-save external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9 32mhz internal oscillator 5 wake-up time from power-down external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9 32mhz internal oscillator 5
68 8386a?avr?07/11 xmega a3u 35.5 i/o pin c haracteristics the i/o pins complies with the jedec lvttl and lvcsmos specification and the high- and low level input and ou tput voltage limits reflect or exceed this specification. table 35-4. i/o pin characteristics symbol parameter condition min typ max units v ih high level input voltage v cc = 3.0 - 3.6v 2 v cc +0.3 v v cc = 2.3 - 2.7v 1.7 v cc +0.3 v cc = 1.6 - 2.7v 0.7*v cc v cc +0.3 v il low level input voltage v cc = 3.0 - 3.6v -0.3 0.8 v cc = 2.3 - 2.7v -0.3 0.7 v cc = 1.6 - 2.7v -0.3 0.2*v cc v oh high level output voltage v cc = 3.0 - 3.6v i oh = -2ma 2.4 3.19 v cc = 2.3 - 2.7v i oh = -1ma 2.0 2.43 i oh = -2ma 1.7 2.37 v ol low level output voltage v cc = 3.0 - 3.6v i ol = 2ma 0.05 0.4 v cc = 2.3 - 2.7v i ol = 1ma 0.03 0.4 i ol = 2ma 0.05 0.7 v ol output low voltage gpio v cc = 3.3v i ol = 15ma 0.41 0.76 v cc = 3.0v i ol = 10ma 0.28 0.64 v cc = 1.8v i ol = 5ma 0.18 0.46 v oh output high voltage gpio v cc = 3.3v i oh = -8ma 2.6 2.86 v cc = 3.0v i oh = -6ma 2.1 2.63 v cc = 1.8v i oh = -2ma 1.4 1.63 i in input leakage current i/o pin <0.001 0.1 a i il input leakage current i/o pin <0.001 0.1 r p i/o pin pull/buss keeper resistor 27 k r rst reset pin pull-up resistor 25 input hysteresis 0.2 v t r pad rise time no load 4 ns slew rate limitation 7
69 8386a?avr?07/11 xmega a3u 35.6 adc characteristics table 35-5. adc characteristics symbol parameter condition (2) min typ max units res resolution 8 12 12 bits conversion time (latency) (res+2)/2+(gain !=0), res = 8 or 2 5 8 clk adc cycles sampling time 1/2 clk adc cycle 0.25 5 s clk adc adc clock frequency max is 1/4 of peripheral clock frequency 100 2000 khz measuring internal signals 100 125 f adc sample rate 100 2000 ksps currlimit = low 100 1500 currlimit = medium 100 1000 currlimit = high 100 500 avcc analog supply voltage v cc - 0.3 v cc + 0.3 v vref reference voltage 1 av cc - 0.6 rin input resistance switched 4.0 k cin input capacitance switched 4.4 pf r aref reference input resistance (leackage only) >10 m c aref reference input capacit ance static load 7 pf start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 after adc flush 1 1 vin input range -0.1 av cc + 0.1 v conversion range differential mode, vinp - vinn -vref vref vin conversion range single ended unsigned mode, vinp - v vref- v inl (1) integral non-linearity 500ksps v cc -1.0v < vref< v cc -0.6v 1.2 2 lsb 1.5 3 2000ksps v cc -1.0v < vref< v cc -0.6v 1.0 2 1.5 3 dnl (1) differential non-linearity 500ksps, guaranteed monotonic v cc -1.0v < vref< v cc -0.6v 0.8 1.2 0.5 1.5 2000ksps, guaranteed monotonic v cc -1.0v < vref< v cc -0.6v 0.8 1.2 0.5 1.5 offset error -2 mv temperature drift <0.01 mv/k operating voltage drift <0.6 mv/v
70 8386a?avr?07/11 xmega a3u notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error num bers are valid under the condition that external vref is used. note: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range. gain error differential mode external reference -1 mv avcc/1.6 10 avcc/2.0 8 bandgap 5 temperature drift <0.02 mv/k operating voltage drift <0.5 mv/v table 35-5. adc characteristics (continued) symbol parameter condition (2) min typ max units table 35-6. adc gain stage characteristics symbol parameter condition min typ max units rin input resistance switched in normal mode 4.0 k cin input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 v cc - 0.6 v propagation delay adc conversion rate 1 clk adc cycles clock rate same as adc 100 1000 khz inl (1) integral non-linearity 500ksps all gain settings 2.0 4 lsb dnl (1) differential non-linearity all gain setting, guaranteed monotonic 0.9 1.5 gain error 1x gain, normal mode -0.8 % 8x gain, normal mode -2.5 64x gain, normal mode -3.5 offset error, input refered 1x gain, normal mode -2 mv 8x gain normal mode -5 64x gain normal mode -4
71 8386a?avr?07/11 xmega a3u 35.7 dac characteristics note: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% output voltage range . table 35-7. dac characteristics symbol parameter condition min typ max units res input resolution 12 bits avref external reference voltage 1.0 v cc -0.6 v r channel dc output impedance 50 linear output voltage range 0.15 av cc -0.15 r aref reference input resistance >10 m c aref reference input capacitance static load 7 pf minimum resistance load 1 k maximum capacitance laod 100 pf 1000 serial resistance 1 nf output sink/source operating within specification av cc /1000 ma safe operation 10 enable, reset to code 0ox inl (1) integral non-linearity vref= ext 1.0v v cc = 1.6v 2.0 3 lsb v cc = 3.6v 1.5 2.5 vref=avcc v cc = 1.6v 2.0 4 v cc = 3.6v 1.5 4 vref=int1v v cc = 1.6v 3.0 v cc = 3.6v 3.0 dnl (1) differential non-linearity vref=ext 1.0v, guaranteed monotonic v cc = 1.6v 1.5 3 v cc = 3.6v 0.6 1.5 vref=avcc, guaranteed monotonic v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 vref=int1v v cc = 1.6v 3.0 v cc = 3.6v 3.0 gain error after calibration <4 gain calibration step size 4 gain calibration drift v ref= ext 1.0v <0.2 mv/k offset error after calibration <1 lsb offset calibration step size 1 fclk conversion rate fout=fclk/4, cload=100pf, max step size 01000 ksps 01000
72 8386a?avr?07/11 xmega a3u 35.8 analog comparator characteristics 35.9 bandgap and internal 1.0v reference characteristics table 35-8. analog comparator characteristics symbol parameter condition min typ max units v off input offset voltage <10 mv i lk input leakage current <1000 pa input voltage range -0.1 av cc + 0.1 v ac startup time 100 s v hys1 hysteresis, none 0 mv v hys2 hysteresis, small mode = high speed (hs) 13 mode = low power (lp) 30 v hys3 hysteresis, large mode = hs 30 mode = lp 60 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 90 100 ns mode = hs 95 v cc = 3.0v, t= 85c mode = lp 200 500 mode = lp 200 64-level voltage scaler integral non-linearity (inl) 0.5 1 lsb current source accuracy after calibration 5 % current source calibration range 4 6 a table 35-9. bandgap and internal 1.0v reference characteristics symbol parameter condition min typ max units startup time as reference for adc or dac 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1 1.01 variation over voltage and temperature 1.0 %
73 8386a?avr?07/11 xmega a3u 35.10 brownout detection characteristics note: 1. bod is calibrated at 85c within bod leve l 0 values, and bod level 0 is the default level. 35.11 external reset characteristics 35.12 power-on reset characteristics table 35-10. brownout detection characteristics (1) symbol parameter condition min typ max units bod level 0 falling vcc 1.62 1.62 1.72 v bod level 1 falling vcc 1.81 bod level 2 falling vcc 2.01 bod level 3 falling vcc 2.21 bod level 4 falling vcc 2.41 bod level 5 falling vcc 2.61 bod level 6 falling vcc 2.81 bod level 7 falling vcc 3.01 t bod detection time continous mode 0,4 s sampled mode 1000 v hyst hysteresis 1.6 % table 35-11. external reset characteristics symbol parameter condition min typ max units t ext minimum reset pulse width 90 1000 ns v rst reset threshold voltage v cc = 2.7 - 3.6v 0.50*v cc v v cc = 1.6 - 2.7v 0.40*v cc table 35-12. power-on reset characteristics symbol parameter condition min typ max units v pot- por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.2 v pot+ por threshold voltage rising v cc 1.3 1.59
74 8386a?avr?07/11 xmega a3u 35.13 flash and eeprom memory characteristics notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 35.14 clock and oscillator characteristics 35.14.1 calibrated 32.768khz internal oscillator characteristics table 35-13. endurance and data retention symbol parameter condi tion min typ max units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 table 35-14. programming time symbol parameter condition min typ (1) max units chip erase 256kb flash, eeprom (2) and sram erase 105 ms 192kb flash, eeprom (2) and sram erase 90 128kb flash, eeprom (2) and sram erase 75 64kb flash, eeprom (2) and sram erase 55 flash page erase 6 page write 6 page writeautomatic page erase and write 12 eeprom page erase 6 page write 6 page writeautomatic page erase and write 12 table 35-15. calibrated 32.768khz internal oscillator characteristics symbol parameter condition min typ max units frequency 32.768 khz factory calibration accuracy t = 85 c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5
75 8386a?avr?07/11 xmega a3u 35.14.2 calibrated 2mhz rc internal oscillator characteristics 35.14.3 calibrated and tunable 32mhz internal oscillator characteristics 35.14.4 32khz internal ulp oscillator characteristics 35.14.5 internal phase locked loop (pll) characteristics table 35-16. calibrated 2mhz internal oscillator characteristics symbol parameter condition min typ max units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.0 2.2 mhz factory calibration accuracy t = 85 c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration stepsize 0.22 table 35-17. calibrated 32mhz internal oscillator characteristics symbol parameter condition min typ max units frequency range dfll can tune to this frequency over voltage and temperature 30 32 55 mhz factory calibration accuracy t = 85 c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 dfll calibration step size 0.23 table 35-18. 32khz internal ulp osc illator characteristics symbol parameter condition min typ max units output frequency 38 khz table 35-19. calibrated 32mhz internal oscillator characteristics symbol parameter condition min typ max units f in input frequnecy output frequnecy must be within f out 0.4 64 mhz f out ouput frequnecy (1) 1. the maximum ouput frequency vs. supply voltage is linear betwe en 1.8v and 2.7v, and can never be higher than 4 times the maximum cpu frequency. 20 32 20 128 start-up time 25 s re-lock time 25
76 8386a?avr?07/11 xmega a3u 35.14.6 external 32.768khz crystal oscillator and tosc characteristics note: 1. see figure 35-2 on page 76 for definition figure 35-2. tosc input capacitance the input capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. 35.14.7 external clock characteristics figure 35-3. external clock drive waveform table 35-20. external 32.768khz crystal osc illator and tosc characteristics symbol parameter condi tion min typ max units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k crystal load capacitance 9.0pf 35 c in_tosc input capacitance between tosc pins normal mode 1.7 pf low power mode 2.2 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768 khz crystal t ch t cl t ck t ch v il1 v ih1 t cr t cf
77 8386a?avr?07/11 xmega a3u note: 1. the maximum frequency vs. supply voltage is linear between 1. 8v and 2.7v, and the same applies for all other parameters with supply voltage conditions. notes: 1. system clock prescalers must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.8v and 2.7v, and the same applies for all other parameters with supply voltage conditions table 35-21. external clock used as system clock without prescaling symbol parameter condition min typ max units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 v cc = 2.7 - 3.6v 3 t ck change in period from one clock cycle to the next 10 % table 35-22. external clock with prescaler (1) for system clock symbol parameter condition min typ max units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) 1.5 t cf fall time (for maximum frequency) 1.5 t ck change in period from one clock cycle to the next 10 %
78 8386a?avr?07/11 xmega a3u 35.15 spi characteristics figure 35-4. spi interface requirements in master mode figure 35-5. spi timing requirements in slave mode msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
79 8386a?avr?07/11 xmega a3u table 35-23. spi timing characteristics and requirements symbol parameter condition min typ max units t sck sck period master (see table 21-4 in xmega au manual) ns t sckw sck high/low width master 0.5*sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5*sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4*t clk per t ssckw sck high/low width slave 2*t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave t clk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8
80 8386a?avr?07/11 xmega a3u 35.16 two-wire interface characteristics table 2-1 describes the requirements for devices connected to the two wire serial bus. the xmega two-wire interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 35-6 . figure 35-6. two-wire interface bus timing t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto table 35-24. two wire serial bus characteristics symbol parameter condition min typ max unit s v ih input high voltage 0.7v cc v cc +0.5 v v il input low voltage 0.5 0.3*v cc v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v ol output low voltage 3ma, sink current 0 0.4 t r rise time for both sda and scl 20+0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 250 t sp spikes suppressed by input filter 0 50 i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl 100khz f scl > 100khz t hd;sta hold time (repeated) start condition f scl 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl 100khz 4.7 f scl > 100khz 1.3 t high high period of scl clock f scl 100khz 4.0 f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl 100khz f scl > 100khz v cc 0.4 v ? 3 ma ---------------------------- 300 ms c b ---------------- -
81 8386a?avr?07/11 xmega a3u notes: 1. required only for f scl > 100khz 2. c b = capacitance of one bus line in pf 3. f per = peripheral clock frequency t hd;dat data hold time f scl 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl 100khz 250 f scl > 100khz 100 t su;sto setup time for stop condition f scl 100khz 4.0 f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl 100khz 4.7 f scl > 100khz 1.3 table 35-24. two wire serial bus characteristics (continued) symbol parameter condition min typ max unit s
82 8386a?avr?07/11 xmega a3u 36. typical characteristics 36.1 active supply current figure 36-1. active supply current vs. frequency f sys = 0 - 1.0mhz external clock, t = 25c figure 36-2. active supply current vs. frequency f sys = 1 - 32mhz external clock, t = 25c 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 100 200 300 400 500 600 700 8 00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ a] 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 14 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] i cc [ma] 2.2 v 1. 8 v
83 8386a?avr?07/11 xmega a3u figure 36-3. active supply current vs. vcc f sys = 1.0mhz external clock figure 36-4. active supply current vs. vcc f sys = 2.0mhz internal oscillator 8 5 c 25 c -40 c 200 300 400 500 600 700 8 00 900 1000 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ a] 8 5 c 25 c -40 c 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ a]
84 8386a?avr?07/11 xmega a3u 36.2 idle supply current figure 36-5. idle supply current vs. frequency f sys = 0 - 1.0mhz, t = 25c figure 36-6. idle supply current vs. frequency f sys = 1 - 32mhz, t = 25c 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 0 20 40 60 8 0 100 120 140 160 1 8 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] icc [ a] 3.3 v 3.0 v 2.7 v 0 1 2 3 4 5 6 04 8 12 16 20 24 2 8 32 fre qu ency [mhz] i cc [ma] 2.2 v 1. 8 v
85 8386a?avr?07/11 xmega a3u figure 36-7. idle supply current vs. vcc f sys = 32.768khz internal oscillator figure 36-8. idle supply current vs. vcc f sys = 2.0mhz internal oscillator 8 5 c 25 c -40 c 2 8 29 30 31 32 33 34 35 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ u a] 8 5 c 25 c -40 c 200 250 300 350 400 450 500 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ a]
86 8386a?avr?07/11 xmega a3u figure 36-9. idle supply current vs. vcc f sys = 32mhz internal oscillator 36.3 power-down supply current figure 36-10. power-down supply current vs. vcc all functions disabled 8 5 c 25 c -40 c 4.0 4.3 4.6 4.9 5.2 5.5 5. 8 6.1 6.4 6.7 2.7 2. 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ a]
87 8386a?avr?07/11 xmega a3u figure 36-11. power-down supply current vs. vcc sampled bod, wdt, rtc from ulp 36.4 pin pull-up figure 36-12. reset and i/o pull-up resistor current vs. reset pin voltage v cc = 1.8v 8 5 c 25 c -40 c 1.1 1.4 1.7 2 2.3 2.6 2.9 3.2 3.5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] i cc [ a] 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 00.20.40.60. 8 1 1.2 1.4 1.6 1. 8 v reset [ v ] i pi n [ a]
88 8386a?avr?07/11 xmega a3u figure 36-13. reset and i/o pull-up resistor current vs. reset pin voltage v cc = 3.0v figure 36-14. reset and i/o pull-up resistor current vs. reset pin voltage v cc = 3.3v 8 5 c 25 c -40 c 0 13 26 39 52 65 7 8 91 104 117 130 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 v reset [ v ] i pi n [ a] 8 5 c 25 c -40 c 0 14 2 8 42 56 70 8 4 9 8 112 126 140 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 3.3 v reset [ v ] i pi n [ a]
89 8386a?avr?07/11 xmega a3u 36.5 pin output voltage vs. sink/source current figure 36-15. i/o pin output voltage vs. source current vcc = 1.8v figure 36-16. i/o pin output voltage vs. source current vcc = 3.0v 8 5 c 25 c -20 c -10 -9 - 8 -7 -6 -5 -4 -3 -2 -1 0 00.20.40.60. 8 1 1.2 1.4 1.6 1. 8 v pi n [ v ] i oh [ma] 8 5 c 25 c -40 c -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 1.5 1.65 1. 8 1.95 2.1 2.25 2.4 2.55 2.7 2. 8 53 v pi n [ v ] i oh [ma]
90 8386a?avr?07/11 xmega a3u figure 36-17. i/o pin output voltage vs. source current vcc = 3.3v figure 36-18. i/o pin output voltage vs. source current t = 25c 8 5 c 25 c -40 c -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 1. 8 1.95 2.1 2.25 2.4 2.55 2.7 2. 8 5 3 3.15 3.3 v pi n [ v ] i oh [ma] 3.6 v 3.3 v 2.7 v 2.2 v 1. 8 v 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 3.3 3.6 -20 -1 8 -16 -14 -12 -10 - 8 -6 -4 -2 0 i pi n [ma] v pi n [ v ]
91 8386a?avr?07/11 xmega a3u figure 36-19. i/o pin output voltage vs. sink current vcc = 1.8v figure 36-20. i/o pin sink current vs. output voltage vcc = 1.8v 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 0246 8 10 12 14 16 1 8 20 i pi n [ma] v pi n [ v ] 8 5 c 8 5 c 25 c 0 2 4 6 8 10 12 14 16 1 8 20 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v pi n [ v ] i oh/iol [ma] -40 c
92 8386a?avr?07/11 xmega a3u figure 36-21. i/o pin sink current vs. output voltage vcc = 3.0v figure 36-22. i/o pin sink current vs. output voltage vcc = 3.3v 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 1 8 20 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 v pi n [ v ] i oh/iol [ma] 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 1 8 20 22 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 v pi n [ v ] i oh/iol [ma]
93 8386a?avr?07/11 xmega a3u 36.6 pin thresholds and hysteresis figure 36-23. i/o pin input threshold voltage vs. v cc t = 25c figure 36-24. i/o pin input hysteresis vs. v cc t = 25c v il v ih 0.5 0.65 0. 8 0.95 1.1 1.25 1.4 1.55 1.7 1. 8 5 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ] 0.1 8 0.195 0.21 0.225 0.24 0.255 0.27 0.2 8 5 0.3 0.315 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] hysteresis [ v ]
94 8386a?avr?07/11 xmega a3u figure 36-25. reset input threshold voltage vs. v cc v ih - i/o pin read as ?1? figure 36-26. reset input threshold voltage vs. v cc v il - i/o pin read as ?0? 8 5 c 25 c -40 c 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ] 8 5 c 25 c -40 c 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] v threshold [ v ]
95 8386a?avr?07/11 xmega a3u 36.7 bod characteristics figure 36-27. bod thresholds vs. temperature bod level = 1.6v figure 36-28. bod thresholds vs. temperature bod level = 2.6v rising v cc falling v cc 1.62 1.622 1.624 1.626 1.62 8 1.63 1.632 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] v bot [ v ] rising v cc falling v cc 2.62 2.625 2.63 2.635 2.64 2.645 2.65 2.655 2.66 2.665 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temeperat u re [c] v bot [ v ]
96 8386a?avr?07/11 xmega a3u 36.8 oscillators 36.8.1 internal 1khz oscillator figure 36-29. 1khz ouput from internal ulp os cillator frequency vs. temperature 36.8.2 32.768khz internal oscillator figure 36-30. 32.768khz internal oscillato r frequency vs . temperature 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 1.09 1.1 1.11 1.12 1.13 1.14 1.15 1.16 1.17 25 30 35 40 45 50 55 60 65 70 75 8 0 8 5 temperat u re [c] fre qu ency [khz] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 32.35 32.4 32.45 32.5 32.55 32.6 32.65 32.7 32.75 32. 8 32. 8 5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz]
97 8386a?avr?07/11 xmega a3u 36.8.3 2mhz internal oscillator figure 36-31. 2mhz internal oscillator ca la calibration step size v cc = 3v figure 36-32. 2mhz internal oscillator frequency vs. temperature 8 5c 25c -40c 0.14 % 0.17 % 0.20 % 0.23 % 0.26 % 0.29 % 0.32 % 0 10203040506070 8 0 90 100 110 120 130 cala step size [ % ] 1.9 8 2 2.02 2.04 2.06 2.0 8 2.1 2.12 2.14 2.16 2.1 8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 temperat u re [c] fre qu ency [mhz] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v
98 8386a?avr?07/11 xmega a3u figure 36-33. 2mhz internal oscillator frequency vs. temperature dfll enabled, from 32.768khz internal oscillator 36.8.4 32mhz internal oscillator figure 36-34. internal 32mhz oscillator frequency vs. temperature dfll disabled 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 1.975 1.97 8 1.9 8 1 1.9 8 4 1.9 8 7 1.99 1.993 1.996 1.999 2.002 2.005 2.00 8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 3.3 v 3.0 v 2.7 v 1. 8 v 31.5 32 32.5 33 33.5 34 34.5 35 35.5 36 36.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz]
99 8386a?avr?07/11 xmega a3u figure 36-35. 32mhz internal oscillator frequency vs. temperature dfll enabled, from 32.768khz internal oscillator figure 36-36. 32mhz internal oscillator cala calibration step size v cc = 3.0v 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 31.6 31.65 31.7 31.75 31. 8 31. 8 5 31.9 31.95 32 32.05 32.1 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 8 5c 25c -40c 0.12 % 0.14 % 0.16 % 0.1 8 % 0.20 % 0.22 % 0.24 % 0.26 % 0.2 8 % 0.30 % 0.32 % 0.34 % 0.36 % 010203040506070 8 0 90 100 110 120 130 cala step size [ % ]
100 8386a?avr?07/11 xmega a3u 36.8.5 32mhz internal oscillator calibrated to 48mhz figure 36-37. 48mhz internal oscillator frequency vs. temperature dfll disabled figure 36-38. 48mhz internal oscillator frequency vs. temperature dfll enabled, from 32.768khz internal oscillator 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 47 4 8 49 50 51 52 53 54 55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz] 3.3 v 3.0 v 2.7 v 2.2 v 1. 8 v 47.45 47.55 47.65 47.75 47. 8 5 47.95 4 8 .05 4 8 .15 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] fre qu ency [mhz]
101 8386a?avr?07/11 xmega a3u 36.9 analog comparator characteristics figure 36-39. ac propagation delay vs. vcc high-speed mode figure 36-40. ac propagation delay vs. temperature high-speed mode 8 5 c 25 c -40 c 40 50 60 70 8 0 90 100 110 120 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] t pd [ns] 3.6 v 2.7 v 1.6 v 40 50 60 70 8 0 90 100 110 120 -45-35-25-15-5 5 15253545556575 8 5 temperat u re [c] t pd [ns]
102 8386a?avr?07/11 xmega a3u figure 36-41. ac current consumption vs. vcc low-power mode mode figure 36-42. ac propagation delay vs. temperature low-spower mode 8 5 c 25 c -40 c 145 150 155 160 165 170 175 1 8 0 1 8 5 190 195 200 205 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] c u rrent cons u mption [ a] 3.6 v 2.7 v 1.6 v 145 150 155 160 165 170 175 1 8 0 1 8 5 190 195 200 205 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] t pd [ns]
103 8386a?avr?07/11 xmega a3u 36.10 adc characteristics figure 36-43. gain error vs. external vref differential mode, v cc = 3.6v, external reference figure 36-44. gain error vs. v cc differential mode, external reference 8 5oc -40oc 25oc -11 -10 -9 - 8 -7 -6 -5 -4 -3 -2 -1 0 1 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 v ref [ v ] gain error [m v ] 8 5oc -40oc 25oc -2 -1. 8 -1.6 -1.4 -1.2 -1 -0. 8 -0.6 -0.4 -0.2 0 0.2 0.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] gain error [m v ]
104 8386a?avr?07/11 xmega a3u figure 36-45. offset vs. external vref differential mode, v cc = 3.6v, external reference figure 36-46. offset vs. v cc differential mode, v cc = 3.6v, external reference. 8 5oc -40oc 25oc -1.1 -1 -0.9 -0. 8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 11.21.41.61. 8 22.22.42.62. 8 3 v ref [ v ] offset [m v ] 8 5oc -40oc 25oc -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] offset [m v ]
105 8386a?avr?07/11 xmega a3u figure 36-47. gain error vs. temperature differential mode, v cc = 3.6v, external reference figure 36-48. inl vs. external vref differential mode, v cc = 3.6v 3 v v ref 2 v v ref 2.5 v v ref 1 v v ref 1.5 v v ref -11 -10 -9 - 8 -7 -6 -5 -4 -3 -2 -1 0 1 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [oc] gain error [m v ] 8 5oc -40oc 25oc 0.7 0. 8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 v ref [ v ] i n l [lsb]
106 8386a?avr?07/11 xmega a3u figure 36-49. dnl vs. external vref differential mode, v cc = 3.6v 36.11 dac characteristics figure 36-50. dnl vs. external vref v cc = 3.6v, external reference 8 5oc -40oc 25oc 0.37 0.42 0.47 0.52 0.57 0.62 0.67 0.72 0.77 0. 8 2 0. 8 7 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 v ref [ v ] d n l [lsb] 8 5oc -40oc 25oc 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.1 1.2 1.3 1.4 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 v ref [ v ] d n l [lsb]
107 8386a?avr?07/11 xmega a3u figure 36-51. inl vs. external vref v cc = 3.6v, external reference 36.12 pdi characteristics figure 36-52. maximum pdi speed vs. vcc 8 5oc -40oc 25oc 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 v ref [ v ] i n l [lsb] 85c 25c -40c 12 14.5 17 19.5 22 24.5 27 29.5 32 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.6 v cc [v] f max [mhz]
108 8386a?avr?07/11 xmega a3u 36.13 reset pin pulsewidth figure 36-53. minimum reset pulse width vs. vcc 8 5 c 25 c -40 c 92 97 102 107 112 117 122 127 132 137 142 147 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 3.2 3.4 3.6 v cc [ v ] t rst [ns]
109 8386a?avr?07/11 xmega a3u 37. errata 37.1 atxmega64a3u, atxmega128a3u , atxmega192a3u, ATXMEGA256A3U 37.1.1 rev. g ? awex fault protection restore is not do ne correct in pattern generation mode 1. awex fault protection restore is not done correctly in pattern generation mode when a fault is detected the outoven register is cleared, and when fault condition is cleared, outoven is restored according to the corresponding enabled dti channels. for common waveform channel mode (cwcm), this has no effect as the outoven is correct after restoring from fault. for pattern generation mode (pgm), outoven should instead have been restored according to the dtilsbuf register. problem fix/workaround for cwcm no workaround is required. for pgm in latched mode, disable the dti c hannels before returning from the fault condi- tion. then, set correct outoven value and enable the dti channels, before the direction (dir) register is written to enable the correct outputs again. for pgm in cycle-by-cycle mode there is no workaround. 37.1.2 rev. a-f not sampled.
110 8386a?avr?07/11 xmega a3u 38. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 38.1 8386a ? 07/11 1. initial revision.
i 8386a?avr?07/11 xmega a3u table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 ordering information .......... .............. ............... .............. .............. ............ 2 2 pinout/block diagram ......... .............. ............... .............. .............. ............ 3 3 overview ............ ................ ................ ............... .............. .............. ............ 4 3.1block diagram ...........................................................................................................5 4 resources .............. .............. .............. ............... .............. .............. ............ 6 4.1recommended reading .............................................................................................6 5 capacitive touch sensing ................. ............... .............. .............. ............ 6 6 avr cpu ............ ................ ................ ............... .............. .............. ............ 7 6.1features ................................................................................................................... .7 6.2overview ................................................................................................................... 7 6.3alu - arithmetic logic unit .......................................................................................8 6.4program flow ............................................................................................................8 6.5register file .............................................................................................................. 8 7 memories ............... .............. .............. ............... .............. .............. ............ 9 7.1features ................................................................................................................... .9 7.2overview ................................................................................................................... 9 7.3flash program memory ...........................................................................................10 7.4data memory ...........................................................................................................11 7.5production signature row .......................................................................................13 7.6user signature row ................................................................................................13 7.7flash and eeprom page size ...............................................................................14 8 dmac - direct memory access controller ............... ................. .......... 15 8.1features ..................................................................................................................1 5 8.2overview .................................................................................................................15 9 event system ........ .............. .............. ............... .............. .............. .......... 16 9.1features ..................................................................................................................1 6 9.2overview .................................................................................................................16 10 system clock and clock options ................ ................. .............. .......... 18 10.1features ................................................................................................................18 10.2overview ...............................................................................................................18
ii 8386a?avr?07/11 xmega a3u 10.3clock options ........................................................................................................19 11 power management and sleep modes ........ ................. .............. .......... 21 11.1features ................................................................................................................21 11.2overview ...............................................................................................................21 11.3sleep modes .........................................................................................................21 12 system control and reset .... .............. .............. .............. .............. ........ 23 12.1features ................................................................................................................23 12.2overview ...............................................................................................................23 12.3reset sources .......................................................................................................23 13 wdt - watchdog timer ......... .............. .............. .............. .............. ........ 25 13.1features ................................................................................................................25 13.2overview ...............................................................................................................25 14 interrupts and programmabl e multi-level interrupt controller .......... 26 14.1features ................................................................................................................26 14.2overview ...............................................................................................................26 14.3interrupt vectors ....................................................................................................26 15 i/o ports ............... ................ .............. ............... .............. .............. .......... 28 15.1features ................................................................................................................28 15.2overview ...............................................................................................................28 15.3output driver .........................................................................................................29 15.4input sensing .........................................................................................................31 15.5alternate port functions ........................................................................................31 16 t/c - 16-bit timer/counter .. .............. ............... .............. .............. .......... 32 16.1features ................................................................................................................32 16.2overview ...............................................................................................................32 17 awex - advanced wavef orm extension ................... ................. .......... 34 17.1features ................................................................................................................34 17.2overview ...............................................................................................................34 18 hi-res - high resolution extension .......... ................ ................. .......... 35 18.1features ................................................................................................................35 18.2overview ...............................................................................................................35 19 rtc - 16-bit real-tim e counter ....... ............... .............. .............. .......... 36 19.1features ................................................................................................................36
iii 8386a?avr?07/11 xmega a3u 19.2overview ...............................................................................................................36 20 usb - universal seri al bus interface ................. .............. ............ ........ 37 20.1features ................................................................................................................37 20.2overview ...............................................................................................................37 21 twi - two wire interface .... .............. ............... .............. .............. .......... 39 21.1features ................................................................................................................39 21.2overview ...............................................................................................................39 22 spi - serial peripher al interface ............ .............. .............. ............ ........ 40 22.1features ................................................................................................................40 22.2overview ...............................................................................................................40 23 usart ............. ................. ................ ................. .............. .............. .......... 41 23.1features ................................................................................................................41 23.2overview ...............................................................................................................41 24 ircom - ir communication module .............. .............. .............. .......... 42 24.1features ................................................................................................................42 24.2overview ...............................................................................................................42 25 aes and des crypto engine .... ................. ................ ................. .......... 43 25.1features ................................................................................................................43 25.2overview ...............................................................................................................43 26 crc - cyclic redundanc y check generator ............ ................. .......... 44 26.1features ................................................................................................................44 26.2overview ...............................................................................................................44 27 adc - 12-bit analog to digi tal converter ....... .............. .............. .......... 45 27.1features ................................................................................................................45 27.2overview ...............................................................................................................45 28 dac - 12-bit digital to an alog converter ................ ................ ............. 47 28.1features ................................................................................................................47 28.2overview ...............................................................................................................47 29 ac - analog comparator .... .............. ............... .............. .............. .......... 48 29.1features ................................................................................................................48 29.2overview ...............................................................................................................48 30 programming and debugging ..... ................ ................. .............. .......... 50
iv 8386a?avr?07/11 xmega a3u 30.1features ................................................................................................................50 30.2overview ...............................................................................................................50 31 pinout and pin functions ................. ............... .............. .............. .......... 51 31.1alternate pin function description ........................................................................51 31.2alternate pin functions .........................................................................................53 32 peripheral module addr ess map ............... ................ ................. .......... 56 33 instruction set summary ... .............. ............... .............. .............. .......... 58 34 packaging information .......... .............. .............. .............. .............. ........ 62 34.164a ....................................................................................................................... .62 34.264m2 .....................................................................................................................6 3 35 electrical characteristics ... .............. ............... .............. .............. .......... 64 35.1absolute maximum ratings* .................................................................................64 35.2dc characteristics ................................................................................................64 35.3operating voltage and frequency ........................................................................66 35.4wakeup time from sleep ........................................................................................67 35.5i/o pin characteristics ...........................................................................................68 35.6adc characteristics .............................................................................................69 35.7dac characteristics .............................................................................................71 35.8analog comparator characteristics .......................................................................72 35.9bandgap and internal 1.0v reference characteristics .........................................72 35.10brownout detection characteristics ....................................................................73 35.11external reset characteristics ............................................................................73 35.12power-on reset characteristics ..........................................................................73 35.13flash and eeprom memory characterist ics .............. ................ ............. ..........74 35.14clock and oscillator characteristics .... ................................................................74 35.15spi characteristics ..............................................................................................78 35.16two-wire interface characteristics .....................................................................80 36 typical characteristics ....... .............. ............... .............. .............. .......... 82 36.1active supply current ............................................................................................82 36.2idle supply current ................................................................................................84 36.3power-down supply current .................................................................................86 36.4pin pull-up .............................................................................................................87 36.5pin output voltage vs. sink/source current .........................................................89 36.6pin thresholds and hysteresis ..............................................................................93
36.7bod characteristics ...............................................................................................95 36.8oscillators ..............................................................................................................9 6 36.9analog comparator characteristics ......................................................................101 36.10adc characteristics ..........................................................................................103 36.11dac characteristics ...........................................................................................106 36.12pdi characteristics ............................................................................................107 36.13reset pin pulsewidth .........................................................................................108 37 errata ........... ................ ................ ................. ................ .............. ........... 109 37.1atxmega64a3u, atxmega128a3u, atxmega192a3u, ATXMEGA256A3U .......109 38 datasheet revision history .. ................ ................. ................ ............. 110 38.18386a ? 07/11 .....................................................................................................110 table of contents.......... ................. ................ ................. ................ ........... i
8386a?avr?07/11 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel : (+81)(3) 3523-3551 fax : (+81)(3) 3523-7581 ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , qtouch ? , qmatrix ? , avr studio ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. windows ? and others are registered trademarks of microsoft corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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